Display Substrate Asymmetric Pixel Layout for Bezel Reduction
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Solution Overview
Problem
Current display technologies face challenges in achieving a high screen-to-body ratio and efficient pixel arrangement, leading to suboptimal display quality and power consumption, particularly in liquid crystal display (LCD) devices.
Innovation Solution
A display substrate design featuring a base with pixel units, data lines, gate lines, and a gate driver circuit, where pixel units are arranged in columns and rows, with TFTs connected to data lines and gate lines, and a gate driver circuit located on one side, optimizing the arrangement to reduce bezel size and enhance display efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixel units are arranged in a conventional grid pattern with TFTs connected to data lines, then the display structure is simple, but the screen-to-body ratio is reduced due to larger bezel size
Solution Approach 1:
The patent employs asymmetric pixel arrangement where pixel units are positioned at different distances from the gate driver circuit side. Specifically, pixel units in columns closer to the gate driver circuit are arranged at a first distance, while pixel units in columns farther away are arranged at a second distance. This asymmetric layout optimizes the screen-to-body ratio by reducing bezel size on one side while maintaining proper signal transmission distances for all pixel units.
2Area of moving object
If pixel units are arranged to maximize screen area, then the screen-to-body ratio increases, but signal transmission quality deteriorates due to varying distances from gate lines
Solution Approach 1:
The patent applies local quality by differentiating the arrangement of pixel units based on their position relative to the gate driver circuit. Pixel units in different column groups are assigned different distances from the gate driver circuit side, allowing each region to be optimized for its specific signal transmission requirements. This ensures that all pixel units receive gate signals within acceptable voltage ranges despite varying distances.
Solution Approach 2:
The patent introduces a dimensional variation in pixel arrangement by positioning pixel units at two different distances from the gate driver circuit side along the column direction. This creates a stepped or tiered arrangement that optimizes both screen area coverage and signal transmission quality by accounting for the spatial dimension of signal propagation.
3Ease of manufacture
If gate driver circuit is integrated on the display substrate, then device complexity increases, but manufacturing precision requirements are reduced
Solution Approach 1:
The patent merges the gate driver circuit directly onto the display substrate, integrating what would traditionally be separate components. The gate driver circuit is positioned adjacent to the pixel units and electrically connected through conductive structures formed during the same manufacturing process, eliminating the need for separate gate driver modules and reducing assembly steps.
Data Source
AI summary
A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different.