Display Substrate Border Reduction via Scan Line Repositioning
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Solution Overview
Problem
Current display technologies face challenges in narrowing the down border of display substrates, particularly in OLED display products, where the down border remains significantly larger than the left and right borders due to limitations in reducing the fan-out or bending regions, affecting the borderless design trend.
Innovation Solution
The display substrate design includes a display region with M pixel rows, featuring a scan signal line and sub-pixels with a pixel drive circuit containing a storage capacitor and multiple transistors, where the second scan signal line is strategically placed close to the display region boundary, and the pixel drive circuit boundary is positioned away from the bonding region, with a distance of 6 μm to 10 μm, optimizing the layout to reduce the down border width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the fan-out region or bending region is reduced to narrow the down border, then the borderless design is improved, but the reliability of signal transmission and device functionality deteriorates
Solution Approach 1:
The patent repositions the second scan signal line from a traditional horizontal arrangement to a vertical arrangement along the display region boundary. This dimensional change allows the signal line to extend into the bonding region without increasing the down border width, thereby maintaining borderless design while ensuring reliable signal transmission to pixels in the display region.
Solution Approach 2:
The second scan signal line acts as an intermediary element that bridges the bonding region and the display region. By positioning this signal line vertically along the boundary and extending it into the bonding region, the patent creates a reliable transmission path that does not require enlarging the fan-out or bending regions, thus resolving the contradiction between border width and signal reliability.
2Shape
If the second scan signal line is positioned close to the display region boundary, then the down border width is reduced, but the complexity of circuit layout increases
Solution Approach 1:
The patent segments the scan signal lines into multiple types: first scan signal lines for controlling transistors away from the boundary, and second scan signal lines for controlling transistors near the boundary. This segmentation allows each signal line type to be optimized independently, reducing overall layout complexity while achieving the narrow border design.
Solution Approach 2:
The patent applies different layout strategies to different regions of the display substrate. In regions close to the display region boundary, the second scan signal line is positioned vertically along the boundary with a distance of 6-10 μm, while in other regions, traditional horizontal arrangements are used. This localized optimization reduces overall complexity by only modifying what is necessary for border reduction.
3Shape
If the pixel drive circuit boundary is positioned 6 μm to 10 μm away from the display region boundary, then the down border is minimized, but the area available for transistor arrangement is reduced
Solution Approach 1:
The patent utilizes the vertical dimension along the display region boundary to arrange the second scan signal line and associated transistors. By extending the second scan signal line vertically into the bonding region and positioning transistors along this vertical path, the design recovers transistor arrangement space that would otherwise be lost due to the narrow horizontal border width.
Solution Approach 2:
The patent creates an asymmetric layout where the second scan signal line and associated transistors are positioned preferentially on one side of the storage capacitor (close to the display region boundary) rather than symmetrically distributed. This asymmetric arrangement optimizes space utilization within the constrained area, allowing sufficient transistor placement while maintaining the narrow 6-10 μm border width.
Data Source
AI summary
Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a display region and a bonding region, wherein the display region includes M pixel rows arranged sequentially, at least one pixel row includes a scan signal line and a plurality of sub-pixels arranged sequentially along an extension direction of the scan signal line, at least one sub-pixel includes a pixel drive circuit connected with the scan signal line, the pixel drive circuit at least includes a storage capacitor and a first transistor as a first initialization transistor, and the scan signal line at least includes a second scan signal line that controls the first transistor to be turned on or off, and in the at least one pixel row, the second scan signal line is arranged on a side of the storage capacitor close to a display region boundary.