Display Substrate Layout for Capacitance-Free Brightness Uniformity
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Solution Overview
Problem
Existing display technologies with camera under panel structures experience uneven brightness due to capacitance formation between transparent connection leads and gate connection electrodes, leading to inconsistent light emission.
Innovation Solution
The display substrate design includes a base substrate with distinct display areas and border areas, featuring connection leads that do not overlap with gate connection electrodes, ensuring electrical connections without capacitance formation, thereby maintaining uniform light brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection leads are arranged to connect pixel driving circuits and light emitting devices, then electrical connection is achieved, but capacitance forms between connection leads and gate connection electrodes causing uneven brightness
Solution Approach 1:
The patent extracts the problematic overlapping region between connection leads and gate connection electrodes by routing connection leads through dedicated openings in the gate connection electrode layer. This separation eliminates the capacitance formation while maintaining electrical connectivity between pixel driving circuits and light emitting devices.
Solution Approach 2:
The patent introduces an intermediary structure (openings in the gate connection electrode layer) that allows connection leads to pass through without forming capacitance. This intermediary solution enables electrical connection while preventing the harmful capacitive coupling effect.
2Area of stationary object
If camera module is integrated under the display panel, then screen-to-body ratio is improved, but capacitance interference occurs between connection leads and gate connection electrodes
Solution Approach 1:
The patent extracts the connection leads from the planar layout and routes them vertically through openings in the gate connection electrode layer. This three-dimensional routing approach eliminates capacitance interference while accommodating the under-display camera module, thereby maintaining high screen-to-body ratio.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical routing approach by creating openings through the gate connection electrode layer. This dimensional change allows connection leads to pass through without lateral overlap, eliminating capacitance interference while preserving the compact under-display camera structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design avoids capacitance-induced current jumps, resulting in improved uniformity of light emission and maintaining consistent brightness across the display area.
Implementation Method 1
orthographic projections of the connection leads on the base substrate do not overlap an orthographic projection of the gate connection electrode on the base substrate... avoids capacitance formation between transparent connection leads and gate connection electrodes
Data Source
AI summary
A display substrate and a display device, the display substrate including first light emitting devices in a first display area, second light emitting devices in a second display area, first pixel driving circuits and second pixel driving circuits, the first pixel driving circuits and the first light emitting devices are correspondingly electrically connected, the second pixel driving circuits at least partially overlap with and are correspondingly electrically connected to the second light emitting devices, and at least one of the second pixel driving circuits has a gate connection electrode. The display substrate further includes connection leads, each of at least some of the connection leads is electrically connected to at least one first pixel driving circuit and one first light emitting device, and orthographic projections of the connection leads and the gate connection electrode on a base substrate do not overlap with each other.