Display Substrate Parasitic Capacitance Uniformity
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Solution Overview
Problem
Current display technologies face challenges in achieving uniform display brightness due to differences in parasitic capacitance values between data lines and control signal lines, leading to uneven brightness across the screen, especially in full-screen display devices with under-camera technology.
Innovation Solution
The display substrate design includes a configuration with varying parasitic capacitance values between data lines and control signal lines, where the difference in capacitance values is minimized to less than 0.15 fF, achieved through strategic placement and sizing of transfer structures and dummy transfer structures, ensuring uniform data voltage distribution across sub-pixel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data lines and control signal lines are arranged in conventional display substrate configurations, then device complexity is reduced and manufacturing is simplified, but parasitic capacitance differences between data lines and control signal lines cause non-uniform display brightness
Solution Approach 1:
The patent applies local quality by differentiating the configuration of data lines in different regions. First data lines include transfer signal lines extending in a first direction with data sub-lines extending in a second direction, while second data lines extend only in the second direction. This localized structural differentiation compensates for parasitic capacitance differences in specific regions, achieving uniform display brightness without complicating the overall device structure.
Solution Approach 2:
The patent changes the geometric parameters of data lines to control parasitic capacitance. By adjusting the orientation and segmentation of data lines (first direction vs. second direction), the parasitic capacitance between data lines and control signal lines is modified. This parameter adjustment ensures that capacitance differences between adjacent sub-pixel regions do not exceed 0.15fF, achieving brightness uniformity through precise parameter control.
2Reliability
If simple data line configurations are used, then device complexity is minimized, but signal interference between data lines and control signal lines causes data voltage deviation
Solution Approach 1:
The patent segments data lines into multiple components: transfer signal lines extending in the first direction and data sub-lines extending in the second direction. This segmentation reduces the length of individual conductors and minimizes their proximity to control signal lines, thereby reducing parasitic capacitance and signal interference. The segmented structure maintains data voltage uniformity without requiring complex shielding or routing arrangements.
3Manufacturing precision
If parasitic capacitance difference between data lines and control signal lines is large, then manufacturing is simpler, but display brightness uniformity deteriorates
Solution Approach 1:
The patent employs asymmetric configuration of data lines to balance parasitic capacitance distribution. First data lines have a T-shaped structure with transfer signal lines in the first direction and data sub-lines in the second direction, while second data lines have a simpler linear structure. This asymmetric design intentionally creates different capacitance characteristics in different regions to compensate for inherent imbalances, achieving overall uniformity without symmetric simplification.
Data Source
AI summary
A display substrate includes: a substrate, light-emitting devices including first and second light-emitting devices, pixel circuits, data lines including first and second data lines, and control signal lines. The pixel circuits include first pixel circuits coupled to the first light-emitting devices and second pixel circuits coupled to the second light-emitting devices. A first data line includes a transfer signal line, and a first data sub-line and a second data sub-line coupled to the transfer signal line. The first data sub-line is coupled to first pixel circuits. A second data line and the second data sub-line are coupled to second pixel circuits. A first capacitance value of a parasitic capacitor between the first data line and a control signal line and a second capacitance value of a parasitic capacitor between the second data line and the control signal line have a difference less than or equal to 0.15 fF.