Display Substrate Capacitor Electrode Overlap Design
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Solution Overview
Problem
The rapid development of high-resolution OLED displays has increased the requirements for the structural design of display substrates, particularly in the arrangement of pixels and signal lines, leading to issues such as increased resistance-capacitance load, signal delay, and voltage drop due to narrower signal lines and overlapping signal lines.
Innovation Solution
The proposed solution involves a display substrate design that includes a plurality of sub-pixels, gate lines, and data lines arranged in an array, with a pixel circuit in each pixel region. The pixel circuit includes a drive sub-circuit, data write sub-circuit, compensation sub-circuit, storage sub-circuit, and light emission control sub-circuit. Additionally, the display substrate incorporates a first capacitor electrode with an extension portion that overlaps with the data line, forming a first capacitor, which improves the stability of the storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If signal lines are made narrower to accommodate high-resolution display requirements, then display resolution is improved, but resistance-capacitance load increases causing signal delay and voltage drop
Solution Approach 1:
The patent introduces a third dimension (vertical stacking) by placing capacitor electrodes above and below the data line in different layers. This spatial arrangement reduces parasitic capacitance between signal lines while maintaining high display resolution, as the capacitor structure extends in the vertical direction rather than occupying horizontal space
2Productivity
If signal lines are made narrower to increase pixel density, then display quality is improved, but parasitic capacitance increases causing signal delay
Solution Approach 1:
The capacitor electrode structure utilizes vertical layering to reduce parasitic capacitance effects that cause signal delay. By positioning electrodes in different vertical layers with selective overlapping, the design minimizes capacitive coupling while maintaining high pixel density in the horizontal plane
3Measurement precision
If signal lines are made narrower to achieve high resolution, then display fineness is improved, but voltage drop increases
Solution Approach 1:
The patent employs vertical stacking of capacitor electrodes to create a distributed capacitance compensation structure. This three-dimensional arrangement provides voltage stability through capacitive coupling without requiring wider horizontal signal lines, thus maintaining display fineness while reducing voltage drop
4Reliability
If capacitor structure is added to improve storage capacitor stability, then signal stability is improved, but device complexity increases
Solution Approach 1:
The patent combines the storage capacitor function with the signal line structure by having capacitor electrodes overlap with the data line. This integration approach improves storage capacitor stability while avoiding the need for completely separate capacitor structures, thus reducing overall device complexity
Solution Approach 2:
The capacitor electrode structure serves multiple functions: it provides storage capacitance, reduces parasitic capacitance between signal lines, and stabilizes voltage levels. This multi-functionality improves storage capacitor stability without proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic capacitance and improves the stability of the storage capacitor, leading to enhanced display performance by minimizing signal delay and voltage drop, thereby maintaining high display quality even at higher resolutions.
Implementation Method 1
a first capacitor electrode Ca and a second capacitor electrode Cb, wherein the first capacitor electrode Ca overlaps with the gate line GL in the direction perpendicular to the base substrate 101 to form a storage capacitor Cst
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel, and the display substrate further includes a first data line extended in the first direction and connected with the first sub-pixel. The sub-pixels further includes a second sub-pixel directly adjacent to the first sub-pixel in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other; and the first capacitor electrode in the first sub-pixel is overlapped with the first data line in a direction perpendicular to the base substrate to provide a first capacitor. The display substrate helps to improve a quality of the display image.