Display Substrate Capping Layer for Short Prevention
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Solution Overview
Problem
Existing display substrate manufacturing methods face challenges in preventing shorts between the common electrode and adjacent metal patterns, which affect the yield and reliability of display devices, particularly in liquid crystal display technologies like IPS and FFS modes.
Innovation Solution
A display substrate design that incorporates a capping layer using a transparent conductive material to cap the second metal pattern, allowing the common electrode and capping layer to be formed through a single etching process, thereby preventing shorts and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the common electrode and capping layer are formed through separate etching processes, then the manufacturing precision may be improved, but the productivity decreases and the risk of shorts increases
Solution Approach 1:
The patent combines the formation of the common electrode and capping layer into a single etching process. The etching pattern simultaneously defines both structures, eliminating the need for separate etching steps. This merging of processes improves productivity while maintaining manufacturing precision through careful design of the etching parameters and mask patterns.
Solution Approach 2:
The patent performs preliminary patterning of the transparent conductive layer to define both the common electrode and capping layer regions before the final etching step. This preliminary action ensures that the subsequent single etching process can accurately form both structures without requiring multiple sequential etching operations, thereby improving both productivity and precision.
2Productivity
If the common electrode and capping layer are formed through one etching process, then the productivity improves, but the manufacturing precision may deteriorate
Solution Approach 1:
The patent applies different local qualities to different regions of the transparent conductive layer. The capping layer region is designed with specific thickness and pattern characteristics, while the common electrode region has different characteristics. This local differentiation allows the single etching process to accurately form both structures with their respective precision requirements.
Solution Approach 2:
The patent resolves the precision conflict by introducing dimensional differentiation in the mask pattern design. The mask pattern includes different opening sizes, shapes, or positions that correspond to the different regions requiring different precision levels. This dimensional variation in the mask allows the single etching process to achieve the required precision for both the common electrode and capping layer.
3Manufacturing precision
If additional etching processes are used to form the common electrode and capping layer separately, then the manufacturing precision improves, but the device complexity increases
Solution Approach 1:
The patent merges the formation of the common electrode and capping layer into a single etching process, thereby reducing the total number of manufacturing steps. This process integration simplifies the manufacturing sequence, reduces process complexity, and eliminates the need for multiple mask alignments and process controls that would otherwise be required.
Solution Approach 2:
The single etching process is designed to perform multiple functions: it forms both the common electrode and the capping layer in one operation. This multi-functionality of the etching step reduces the overall process complexity by eliminating the need for separate dedicated etching processes for each structure.
Data Source
AI summary
A display substrate includes a base substrate, a first metal pattern, a second metal pattern, a first transparent conductive layer and a second transparent conductive layer. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode connected to the gate line. The second metal pattern includes a data line crossing the gate line, a source electrode connected to the data line and a drain electrode being spaced apart from the source electrode. The first transparent conductive layer includes a capping layer capping the second metal pattern and a common electrode formed in a pixel area. The second transparent conductive layer includes a pixel electrode having a plurality of openings, contacting the capping layer capping the drain electrode, and facing the common electrode.