Display Substrate Column Inversion Design

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Solution Overview

Problem

Existing dual-gate pixel structures face challenges in using column inversion without causing charging differences between columns, leading to poor vertical lines and increased power consumption.

Innovation Solution

A display substrate design featuring gate-line groups with two gate lines, alternately arranged data lines, and transistors connected in a specific manner to allow for column inversion without reducing the opening rate, while reducing the number of data lines and ICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If dual-gate pixel structure with column inversion is used, then the number of data lines and ICs is reduced, but charging differences between columns occur causing poor vertical lines

Engineering Contradiction:
Improvenumber of data lines and ICsVSAvoidvertical line quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The pixel array is divided into multiple columns, each column connected to a separate data line. By segmenting the data transmission paths, the patent enables independent control of charging for each column, thereby eliminating charging differences between columns while maintaining the reduced data line structure of dual-gate pixels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different potential distributions to different columns through the data lines. Each column can have customized local quality characteristics (different charging potentials), allowing column inversion to be implemented without causing uniform charging differences across all columns, thus maintaining vertical line quality.

Inventive Principle:
Principle #3Local quality

2Device complexity

If dual-gate pixel structure is used, then the number of ICs is reduced, but power consumption increases

Engineering Contradiction:
Improvenumber of ICsVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic potential distribution across columns through the data lines, enabling column inversion where adjacent columns have opposite polarity. This periodic action allows the system to reduce power consumption by utilizing the natural alternating pattern while maintaining the reduced IC configuration of dual-gate pixels.

Inventive Principle:
Principle #19Periodic action

3Reliability

If traditional single-gate structure is used, then vertical line quality is maintained, but the number of ICs increases

Engineering Contradiction:
Improvevertical line qualityVSAvoidnumber of ICs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple ICs into a single IC by using the data lines to provide both data transmission and column inversion control. The data lines serve dual purposes: transmitting pixel data and controlling the inversion pattern across columns, thereby reducing the number of ICs while maintaining vertical line quality through proper potential distribution.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12332526B2Display substrate, display panel and display device
Publication Date: 2025.06.17 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US12332526B2 patent drawing
  • US12332526B2 patent drawing
  • US12332526B2 patent drawing

AI summary

Disclosed are a display substrate, a display panel and a display device. The display substrate includes: a base substrate, multiple gate-line groups, multiple data lines, the multiple data line include: first type of data lines and second type of data lines alternately arranged along the first direction; multiple transistors, transistors in the same sub-transistor group are connected with the same gate line, transistors in adjacent sub-transistor groups are connected with different gate lines, and transistors of the same sub-transistor group are connected with different data lines; multiple pins, the multiple pins include: first type of pins and second type of pins alternately arranged along the first direction; two adjacent first type of data lines are connected with a same first type of pin, and adjacent second type of data lines are connected with a same second type of pin.