Display Substrate Connection Structures for High Refresh Rate

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Solution Overview

Problem

Medium and large size display products face challenges in achieving high refresh rates due to load limitations, which are exacerbated by the need for thick insulating layers that can affect the flatness of light-emitting functional layers and reduce aperture ratios, thereby shortening the service life of the display.

Innovation Solution

A display substrate design that includes a base substrate with sub-pixels featuring a sub-pixel driving circuit and a light-emitting element, where connection structures are strategically located in non-aperture regions to minimize space occupation and maintain aperture ratio, using deep via-hole structures and conductive connection portions to reduce load and enhance electrical conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If thick insulating layers are used to reduce load in medium and large size display products, then the load capacity is improved, but the flatness of light-emitting functional layers deteriorates and aperture ratio is reduced

Engineering Contradiction:
Improveload capacityVSAvoidflatness of light-emitting functional layers
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent transitions from planar connection structures to three-dimensional stacked structures. Connection structures are arranged in multiple layers (first connection structure in first organic layer, second connection structure in second organic layer) with vertical stacking, allowing electrical connections to pass through multiple insulating layers via via-hole structures without requiring thicker single-layer insulating layers. This dimensional transition maintains load capacity while preserving flatness and aperture ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested structures where connection structures are embedded within insulating layers. The first and second connection structures are nested within the first and second organic layers respectively, with via-hole structures penetrating through the insulating layers to establish vertical electrical connections. This nesting approach allows thick insulating layers to provide adequate load isolation while maintaining the flatness required for light-emitting functional layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If connection structures are placed in non-aperture regions, then the aperture ratio is improved, but the layout complexity increases

Engineering Contradiction:
Improveaperture ratioVSAvoidlayout complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the connection structures into multiple independent components distributed across different layers and regions. The first connection structure is located in the first non-aperture region within the first organic layer, while the second connection structure is located in the second non-aperture region within the second organic layer. This segmentation allows each connection structure to be independently optimized and routed, reducing overall layout complexity while maximizing aperture ratio.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent resolves layout complexity by transitioning from two-dimensional planar arrangement to three-dimensional stacked arrangement. Connection structures that would otherwise need to be arranged in complex overlapping patterns in the same plane are instead distributed across multiple vertical layers (first organic layer and second organic layer), simplifying the lateral layout while maintaining electrical connectivity and maximizing aperture area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If deep via-hole structures are used to reduce load, then the electrical conductivity is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the electrical connection path into multiple via-hole structures distributed across different insulating layers. Instead of requiring single extremely deep via-holes penetrating through all insulating layers, the connection is divided into sequential via-hole segments (first via-hole structure in first organic layer, second via-hole structure in second organic layer). Each via-hole segment can be manufactured with standard depth and diameter, reducing manufacturing complexity while maintaining overall electrical conductivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent distributes the electrical connection function across multiple vertical layers rather than relying on single deep via-holes. The stacked arrangement of connection structures in the first and second organic layers creates multiple parallel conduction paths through the insulating layers. This multi-dimensional conduction network achieves equivalent or superior electrical conductivity compared to single deep via-holes, while each individual via-hole structure remains manufacturable with standard processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250098447A1Display substrate and display device
Publication Date: 2025.03.20 HEFEI BOE ZHUOYIN TECH CO LTD
  • US20250098447A1 patent drawing
  • US20250098447A1 patent drawing
  • US20250098447A1 patent drawing

AI summary

A display substrate and a display device are provided. The display substrate includes: a base substrate, data lines and sub-pixels on the base substrate. The sub-pixels include a sub-pixel driving circuit and a light-emitting element including a first electrode. The sub-pixel driving circuit includes a driving transistor and a data writing transistor having a first electrode coupled to the data line through a second connection structure. A second electrode of the driving transistor is coupled to the first electrode through a first connection structure. The first and second connection structures are in a non-aperture region of the sub-pixel. Orthographic projections of the first and second connection structures onto the base substrate are arranged along a first direction. An orthographic projection of the second connection structure onto the base substrate and an aperture region of the sub-pixel are along a second direction which intersects the first direction.