Display Substrate Reducing Crosstalk via Layered Electrode Design
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Solution Overview
Problem
Conventional ultra-narrow bezel or full screen LCDs suffer from 'V' shaped display abnormalities and crosstalk due to asymmetrical parasitic capacitance effects between scanning lines and data lines, leading to poor display quality.
Innovation Solution
A display substrate design with second scanning lines parallel to data lines, common electrodes, and pixel electrodes in different layers, where the orthographic projections of data lines and second scanning lines overlap pixel electrodes, reducing parasitic capacitance and ensuring symmetric signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ultra-narrow bezel or full screen LCD structure is used, then screen area is increased, but parasitic capacitance between scanning lines and data lines increases causing crosstalk and display abnormalities
Solution Approach 1:
The patent introduces a third dimension by positioning the common electrode in a different layer than the scanning lines and data lines. Specifically, the common electrode is located on the side of the scanning lines and data lines away from the base substrate, while the pixel electrode is on the side proximal to the base substrate. This vertical stacking arrangement in different layers reduces the parasitic capacitance between the scanning lines and data lines by separating them spatially across multiple dimensions.
2Area of stationary object
If scanning lines and data lines are positioned to maximize screen area, then display coverage is improved, but asymmetrical parasitic capacitance effects cause V shaped display abnormalities
Solution Approach 1:
The patent employs asymmetry in the vertical stacking arrangement where the common electrode and pixel electrode are positioned on opposite sides of the scanning lines and data lines relative to the base substrate. This asymmetric configuration creates a symmetric electrical field distribution that compensates for the asymmetric physical layout, thereby eliminating the V-shaped display abnormalities caused by asymmetrical parasitic capacitance effects.
Solution Approach 2:
The common electrode acts as an intermediary element between the scanning lines and the pixel electrode. By positioning the common electrode on the side of the scanning lines away from the base substrate and the pixel electrode on the side proximal to the base substrate, the common electrode mediates the electrical field distribution and reduces the asymmetrical parasitic capacitance effects that cause display abnormalities.
3Ease of manufacture
If data lines and scanning lines are placed in spacer regions between pixel electrodes, then manufacturing is simplified, but crosstalk between lines increases
Solution Approach 1:
The patent resolves the crosstalk issue by utilizing the vertical dimension. While the data lines and scanning lines remain in the spacer regions between pixel electrodes for manufacturing simplicity, the common electrode is positioned in a different layer on the side of the scanning lines away from the base substrate. This three-dimensional arrangement maintains manufacturing simplicity while reducing crosstalk through spatial separation across multiple layers.
Data Source
AI summary
An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.