Display Substrate Trace Layout for ESD Lead-Out in Under-Display Cameras
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Solution Overview
Problem
The production process of pixel circuits in display substrates using Full Display with Camera technology faces a significant Electro-Static Discharge (ESD) risk due to static electricity accumulation, leading to yield loss.
Innovation Solution
A display substrate design with a circuit structure layer and light emitting structure layer, featuring interconnected traces that form static electricity lead-out paths from the display region to the peripheral region, including integral and double-layer trace structures, and conductive layers with specific electrical connections to effectively dissipate static electricity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If Full Display with Camera technology is implemented to increase screen-to-body ratio, then display area is improved, but static electricity accumulation risk increases leading to ESD damage
Solution Approach 1:
The patent converts the harmful static electricity accumulation into a beneficial discharge path by designing conductive trace structures that intentionally guide static electricity from the display region to the peripheral region, where it can be safely dissipated. The traces act as controlled pathways that transform the potential damage into a safe discharge mechanism.
Solution Approach 2:
The conductive traces serve as intermediary elements between the display region and peripheral region, mediating the static electricity discharge process. These traces provide a controlled intermediate path that allows static electricity to travel from sensitive display areas to safe peripheral discharge points without causing damage to pixel circuits or other components.
2Reliability
If trace structures are added to create static electricity lead-out paths, then ESD protection is improved, but device complexity increases
Solution Approach 1:
The conductive traces are designed to serve multiple functions: they provide static electricity discharge paths while also maintaining electrical connections for pixel circuit operation. By making the traces multi-functional, the patent avoids adding separate dedicated ESD protection structures, thereby reducing overall device complexity.
Solution Approach 2:
The patent merges the ESD protection function with the existing conductive trace structures used for pixel circuit connections. Instead of creating separate ESD protection pathways, the design combines both functions into unified trace structures that serve dual purposes, simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the ESD risk, improving the production yield by providing efficient static electricity discharge paths, thus enhancing the reliability and efficiency of the display substrate manufacturing process.
Implementation Method 1
The circuit structure layer includes a plurality of pixel circuits located in the first display region, at least one first trace extending along a first direction, at least one second trace extending along a second direction, and at least one third trace located in the peripheral region. At least one first trace and at least one second trace of the first display region are electrically connected. At least one third trace is electrically connected with at least one of following: at least one first trace and at least one second trace.
Data Source
AI summary
Disclosed is a display substrate, including a base substrate (100), a circuit structure layer disposed on the base substrate (100), and a light emitting structure layer. The circuit structure layer includes a plurality of pixel circuits located in a first display region (A1), at least one first trace 231 extending along a first direction (D1), at least one second trace 232 extending along a second direction (D2), and at least one third trace located in a peripheral region (BB). The at least one first trace (231) is electrically connected with the at least one second trace (232) and the at least one third trace is electrically connected with at least one of following; the at least one first trace (231) and the at least one second trace (232).