Display Substrate Fanout Layout for Narrower Lower Borders

The patent transitions from a planar fanout arrangement to a three-dimensional stacked architecture by introducing multiple conductive layers. Data fanout lines are distributed across different layers (first conductive layer, second conductive layer, third conductive layer) with vertical stacking, allowing signals to be transmitted through the thickness dimension rather than expanding the horizontal fanout area, thus reducing the lower border width while maintaining signal transmission reliability

The patent implements a nested wiring structure where data fanout lines are arranged in multiple nested conductive layers. The first conductive layer contains lead wires and first data fanout lines, the second conductive layer contains second data fanout lines, and the third conductive layer contains data lines. This nested layering allows compact packaging of multiple signal paths within the same horizontal footprint, reducing the required fanout area and enabling narrower borders

The patent segments the wiring structure into distinct conductive layers, with each layer dedicated to specific signal transmission functions. The first conductive layer handles lead wire connections, the second conductive layer handles intermediate fanout, and the third conductive layer handles final data line connections. This segmentation allows each layer to be optimized independently for its specific function, simplifying the manufacturing process while achieving compact overall structure

The patent introduces insulating layers as intermediaries between conductive layers to provide electrical isolation and structural support. These insulating layers act as mediators that enable the multi-layer wiring structure to function properly while maintaining manufacturing feasibility. The insulating layers separate the conductive layers electrically and mechanically, making the complex multi-layer structure manageable and manufacturable