Display Substrate Gate Line Layout for High-Mobility TFT Circuits

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Solution Overview

Problem

Thin-film transistor (TFT) circuits in display devices face challenges with low charge mobility when using amorphous silicon and non-uniform threshold voltage when using polysilicon, requiring additional compensation circuits.

Innovation Solution

The display device incorporates a specific structure with a first and second active pattern, gate electrodes, and a contact portion penetrating an insulating layer, where the second gate electrode is electrically connected to a gate line, and the second active pattern and gate electrode partially overlap, with optimized dimensions to enhance circuit characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If amorphous silicon is used for the active layer of TFT, then the manufacturing process is simpler, but charge mobility is low making high-speed operation difficult

Engineering Contradiction:
Improveease of manufactureVSAvoidcharge mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent employs a dual-layer active layer structure combining amorphous silicon and polysilicon. The amorphous silicon layer provides ease of manufacture through low-temperature processing, while the polysilicon layer contributes high charge mobility. This composite structure allows the device to achieve both manufacturing simplicity and high-speed operation by leveraging the complementary properties of the two materials.

Inventive Principle:
Principle #40Composite materials

2Speed

If polysilicon is used for the active layer of TFT, then charge mobility is improved, but threshold voltage becomes non-uniform requiring additional compensation circuits

Engineering Contradiction:
Improvecharge mobilityVSAvoidcircuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent uses a composite active layer structure where the amorphous silicon layer provides uniform threshold voltage characteristics, eliminating the need for compensation circuits, while the polysilicon layer delivers high charge mobility. This material combination resolves the contradiction by allowing the device to achieve both high speed operation and uniform electrical characteristics without additional circuit complexity.

Inventive Principle:
Principle #40Composite materials

3Productivity

If the contact portion width is reduced to increase pixel density, then more pixels can be accommodated, but manufacturing precision requirements increase

Engineering Contradiction:
Improvepixel densityVSAvoidcontact portion width control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent extends the contact portion in the second direction (vertical direction in the cross-section) to increase its effective area for electrical connection. This dimensional extension allows the contact portion to maintain sufficient electrical connection capability even when its width in the first direction is reduced, thereby enabling higher pixel density without proportionally increasing manufacturing precision requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12108642B2Display substrate including third gate line between first gate electrode and second active pattern
Publication Date: 2024.10.01 SAMSUNG DISPLAY CO LTD
  • US12108642B2 patent drawing
  • US12108642B2 patent drawing
  • US12108642B2 patent drawing

AI summary

A display device includes: a first active pattern above a substrate; a first gate electrode above the first active pattern; a second active pattern above the first gate electrode; a second gate electrode above the second active pattern; and a first gate line between the first gate electrode and the second active pattern and extending in a first direction, wherein the second gate electrode is electrically connected to the first gate line through a contact portion penetrating an insulating layer between the second gate electrode and the first gate line, wherein, in a plan view, a width of the second gate electrode surrounding the contact portion is 1.5 micrometers (μm) or greater.