Display Substrate Gate Line Reduction via Pixel Group Segmentation
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Solution Overview
Problem
Current TFT-LCD technologies face challenges in reducing the number of gate lines, which increases costs and power consumption, and enlarges the bezel, while also limiting the resolution and effective display area due to the higher number of gate lines required for higher vertical resolution.
Innovation Solution
A display substrate with pixel units divided into groups, where each group shares a gate line, reducing the number of gate lines needed while maintaining or increasing vertical resolution, and a driving method that applies active levels to control signal lines and data lines to suppress flicker, allowing for a more efficient and cost-effective display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of gate lines is increased to achieve higher vertical resolution, then the image definition is improved, but the cost and power consumption increase
Solution Approach 1:
The pixel array is divided into multiple groups along the column direction, with each group containing n rows of pixel units. Each group shares a common gate line, segmenting the control function across multiple control signal lines while reducing the total number of gate lines required. This segmentation allows high vertical resolution to be achieved without proportionally increasing the number of gate lines.
Solution Approach 2:
The patent introduces control signal lines that extend along the row direction, perpendicular to the traditional gate line orientation. This dimensional change allows control signals to be applied row-by-row within each pixel group, enabling multiple rows to share gate lines while maintaining independent control capability, thus resolving the contradiction between resolution and gate line count.
2Measurement precision
If the number of gate lines is increased to achieve higher vertical resolution, then the image definition is improved, but the bezel size increases
Solution Approach 1:
By segmenting the pixel array into groups that share gate lines, the patent reduces the total number of gate lines required. This reduction directly decreases the area occupied by fanout lines in the bezel region, thereby shrinking the bezel size while maintaining high vertical resolution through the group-based control architecture.
3Measurement precision
If the number of gate lines is increased to achieve higher vertical resolution, then the image definition is improved, but the power consumption increases
Solution Approach 1:
Multiple rows of pixel units within each group share common gate lines, merging the control function for these rows. This merging reduces the total number of gate lines and their associated driving circuits, thereby reducing power consumption while maintaining the ability to control each pixel individually through the combination of shared gate lines and row-specific control signal lines.
Solution Approach 2:
The patent employs periodic scanning of control signal lines through the pixel groups, activating one row at a time within each group. This periodic action allows multiple rows to share gate lines temporally, reducing the number of simultaneously active gate lines and thus reducing power consumption while maintaining high vertical resolution.
4Productivity
If the number of gate lines is reduced to lower costs and power consumption, then the manufacturing efficiency is improved, but the vertical resolution decreases
Solution Approach 1:
The patent segments the control architecture into shared gate lines and row-specific control signal lines. This segmentation allows fewer gate lines to control multiple rows within each group, reducing manufacturing complexity and cost, while the additional control signal lines maintain the ability to address each pixel individually, preserving high vertical resolution.
Solution Approach 2:
By introducing control signal lines extending in the row direction (perpendicular to gate lines), the patent adds a dimensional control mechanism that compensates for the reduced number of gate lines. This dimensional change enables high vertical resolution to be achieved with fewer gate lines, improving manufacturing efficiency without sacrificing resolution.
Data Source
AI summary
The present disclosure provides a display substrate such that each pixel unit of the display substrate includes a switching circuit and a control circuit, and the switching circuit is connected to a corresponding gate line, a control circuit of a respective pixel unit, and a corresponding pixel electrode. The control circuit is configured to transmit a data signal on a corresponding data line to a switching circuit of the respective pixel unit under control of a corresponding control signal line, and n is an integer not less than 2. The present disclosure further provides a display device including the above display substrate and a driving method for the above display substrate.