Display Substrate Signal Routing for Synchronized Gate Control
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Solution Overview
Problem
Existing display technologies face issues with synchronization of gate control signals on opposite sides of the display region, leading to abnormal display due to uneven signal output from different driver chips, which can result in inconsistent signal durations and incomplete data writing.
Innovation Solution
The display substrate design includes multiple signal lines connected to different driver chips through signal access pins, ensuring consistent output signals by integrating sub-signal lines and using multi-layer wiring to reduce resistance and static electricity accumulation, with gate drive circuits strategically positioned to avoid interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If driver chips are placed on opposite sides of the display region to reduce connection length, then signal transmission speed is improved, but gate control signal synchronization deteriorates due to uneven signal output
Solution Approach 1:
The patent merges the gate control signal lines from opposite sides into a common connection line that routes both signals through a centralized gate drive circuit. This ensures that both driver chips receive identical gate control signals simultaneously, resolving the synchronization issue while maintaining the speed benefit of having driver chips on opposite sides.
Solution Approach 2:
The patent introduces a gate drive circuit as an intermediary component that receives master clock signals and generates synchronized gate control signals for both driver chips. This intermediary ensures that despite the physical separation of driver chips on opposite sides, the gate control signals remain synchronized through the mediating gate drive circuit.
2Area of moving object
If signal lines are made thinner to reduce pixel occupation area, then display resolution is improved, but signal transmission stability deteriorates due to increased resistance
Solution Approach 1:
The patent transitions from single-layer signal lines to multi-layer wiring structures, adding the vertical dimension to the signal transmission path. This allows thin signal lines in the horizontal plane (maintaining high resolution) to be reinforced by multiple conductive layers stacked vertically, thereby reducing overall resistance and improving signal transmission stability.
Solution Approach 2:
The patent uses composite wiring structures combining multiple conductive layers with different materials and properties. By stacking different conductive materials and configurations, the system achieves both low resistance (for stability) and minimal horizontal space occupation (for high resolution).
Data Source
AI summary
Disclosed is a display substrate including a base substrate, at least one first signal line, and multiple signal access pins. The base substrate includes a display region and a peripheral region located at a periphery of the display region. The peripheral region includes a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region which are communicated sequentially. The first signal line is located in the peripheral region and includes at least two sub-signal lines connected with each other. The multiple signal access pins are located in a signal access region. Each sub-signal line of the first signal line extends to the signal access region and is connected with at least one signal access pin in the signal access region so as to be connected with a driver chip through the signal access pin.