Display Substrate GOA Signal Line Stacking to Reduce Resistance and Heat
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Solution Overview
Problem
As display panel resolution increases, accommodating the growing number of integrated circuits within the limited space of the display panel becomes challenging, particularly due to the complexity of gate-on-array (GOA) areas, leading to issues with heat generation and resistance in signal lines.
Innovation Solution
A display substrate design with a GOA area outside the display area, where signal lines like clock, start, and power lines are partially overlapping with other signal lines or power lines, and are electrically connected in parallel with light shielding layers through vias to reduce resistance and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display panel increases, then the display quality is improved, but the density of integrated circuits increases making it difficult to accommodate them in the margins
Solution Approach 1:
The patent introduces a third signal line layer above the first and second signal line layers, creating a three-dimensional signal line structure. This vertical stacking allows additional signal lines to be routed in the GOA area without increasing lateral congestion, thereby accommodating higher integrated circuit density while maintaining display resolution.
2Measurement precision
If more signal lines are added to accommodate higher resolution, then the display quality is improved, but the resistance and heat generation in signal lines increase
Solution Approach 1:
The patent merges multiple signal line functions into a integrated signal line structure where the third signal line layer is electrically connected to both first and second signal line layers through conductive plugs. This consolidation allows signal distribution through multiple parallel paths, reducing overall resistance and heat generation while supporting higher resolution displays.
Solution Approach 2:
By adding a vertical dimension with the third signal line layer, the patent creates additional current pathways that reduce resistance. The stacked configuration allows signals to be distributed through multiple layers simultaneously, reducing current density and heat generation in individual signal lines while maintaining high display resolution.
3Area of stationary object
If the margin of display panel is reduced to accommodate more circuits, then the area for integrated circuits is improved, but the space for signal lines becomes more constrained
Solution Approach 1:
The patent resolves signal line routing complexity by transitioning from a planar two-layer structure to a three-layer vertical structure. The third signal line layer provides additional routing capacity above the existing layers, allowing complex signal distributions to be achieved within the constrained GOA area without increasing lateral signal line density.
Data Source
AI summary
A display substrate having a display area and a gate-on-array (GOA) area outside the display area is provided. The display substrate includes a base substrate; a plurality of GOA signal lines on the base substrate and in the GOA area; and a first signal line in the GOA area, at least a portion of the first signal line being on a side of the plurality of GOA signal lines away from the base substrate. An orthographic projection of the first signal line on the base substrate at least partially covers an orthographic projection of at least one of a first clock signal line, a second clock signal line, a start signal line, a high voltage power line, or a low voltage power line on the base substrate.