Display Substrate Mesh Power Lines for High-Resolution Signal Stability
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Solution Overview
Problem
The increased pixel density and reduced line width in high-resolution OLED displays lead to signal line resistance-capacitance issues, causing signal delay, voltage drop, and parasitic capacitance, which affect display quality.
Innovation Solution
A display substrate design with optimized pixel circuit arrangements, including a 2T1C pixel circuit with compensation sub-circuits and a mesh-shaped power line structure, reduces signal line resistance and parasitic capacitance, and stabilizes the storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased and line width is reduced to achieve high-resolution display, then display resolution is improved, but signal line resistance-capacitance issues worsen causing signal delay and voltage drop
Solution Approach 1:
The power supply network is segmented into multiple power lines arranged in a mesh pattern, dividing the current path into smaller segments. This reduces the resistance and capacitance of individual signal lines while maintaining overall power delivery capability, thereby improving signal transmission quality without sacrificing display resolution.
Solution Approach 2:
The patent transitions from traditional linear or grid power line arrangements to a mesh-shaped three-dimensional network structure. This dimensional enhancement allows current to flow through multiple parallel paths, reducing effective resistance and distributing capacitive load, thus mitigating signal delay and voltage drop in high-resolution displays.
2Measurement precision
If pixel density is increased, then display resolution is improved, but parasitic capacitance increases causing signal delay
Solution Approach 1:
The mesh-shaped power line structure segments the parasitic capacitance into multiple smaller capacitive elements distributed across the mesh network. This segmentation reduces the effective parasitic capacitance affecting any single pixel circuit, thereby minimizing signal delay while maintaining high display resolution.
3Measurement precision
If line width is reduced to accommodate higher pixel density, then display resolution is improved, but signal line resistance increases causing voltage drop
Solution Approach 1:
The mesh structure segments the voltage delivery path into multiple short segments connected in parallel. Even though individual line segments have reduced width and higher resistance, the parallel configuration reduces total effective resistance, maintaining voltage stability across the display while enabling higher pixel density.
Solution Approach 2:
Multiple thin power line segments are merged into a unified mesh network that functions as a single low-resistance power delivery system. The combined effect of parallel current paths compensates for the high resistance of individual narrow lines, ensuring stable voltage supply to high-density pixels.
Data Source
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Figure 1B
Figure 1C
AI summary
A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel and a second sub-pixel which are directly adjacent in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other. The display substrate helps can reduce cross talk between signal lines so as to improve a display quality.