Display Substrate Shift Register Topology for Narrow-Frame Noise Reduction
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Solution Overview
Problem
Existing display panel designs face challenges in efficient space utilization and signal interference due to the complex arrangement of transistors in the shift register units, which affects the narrow frame design and display quality.
Innovation Solution
A display substrate with a shift register unit design that includes specific arrangements of transistors and signal lines, utilizing a base substrate with optimized transistor layouts and signal connections to reduce space congestion and parasitic capacitance, featuring a first and second clock signal line, input, output, and control circuits, and noise reduction transistors with angled and layered connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors in shift register units are arranged in conventional layouts, then circuit functionality is achieved, but space utilization is inefficient and signal interference increases
Solution Approach 1:
The patent applies dimensional arrangement by positioning transistors at different spatial locations (first, second, third, and fourth positions around the capacitor) rather than linear arrangement. This multi-dimensional layout optimizes space utilization while maintaining electrical connectivity and reducing parasitic capacitance between adjacent transistors.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element positioned between transistors to couple signals while isolating them from direct interference. The capacitor acts as a mediator that transfers necessary signals while blocking harmful parasitic capacitance effects, thereby reducing signal interference in the compact layout.
2Length of stationary object
If transistors are positioned closer to reduce frame size, then narrow frame design is enabled, but parasitic capacitance increases affecting display quality
Solution Approach 1:
The patent applies local quality by assigning specific positions to different transistor types (first transistor at first position, second transistor at second position, etc.) around the capacitor. Each transistor is strategically placed in a location that minimizes its parasitic capacitance contribution while maintaining functional connectivity, thereby reducing overall parasitic effects in the compact design.
Solution Approach 2:
The patent performs preliminary arrangement of transistors in optimized positions before final circuit operation. The transistor positions are pre-calculated and pre-positioned around the capacitor to minimize parasitic capacitance from the outset, rather than allowing parasitic effects to accumulate during operation. This preliminary optimization enables compact framing without sacrificing display quality.
Data Source
AI summary
A display substrate and an electronic device are provided. The display substrate includes a base substrate, including a display region and a peripheral region on at least one side of the display region; and a shift register unit and a first clock signal line in the peripheral region of the base substrate, wherein the first clock signal line extends along a first direction on the base substrate, and is connected to a first clock signal terminal to be configured to provide a first clock signal to the shift register unit; the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit; the output control circuit includes an output control transistor and a first capacitor, and the output circuit includes an output transistor and a second capacitor.