Display Substrate Capacitance Compensation for Notch Mura
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Solution Overview
Problem
Display panels with special-shaped structures, such as a notch design, face issues of display unevenness (Mura) due to differences in gate line signals between pixels on either side of the notch and other display regions.
Innovation Solution
A display substrate design incorporating a capacitance compensation region between the display and notch regions, featuring a semiconductor structure, first and second metal structures, and vias to form capacitors, ensuring overlap projections and vias are spaced appropriately to compensate for loading capacitance and maintain display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a notch design is implemented in the display screen to reserve design space for components, then the screen-to-body ratio is improved, but display unevenness (Mura) occurs due to gate line signal differences
Solution Approach 1:
The gate line is divided into two separate gate lines (first gate line and second gate line) that extend into the notch region from opposite sides. This segmentation allows independent control and compensation of signal characteristics in different regions, enabling uniform display performance across the entire screen including the notch area.
Solution Approach 2:
Different gate lines are designed with different characteristics (widths, positions) to compensate for local variations in the notch region. The first and second gate lines have specifically designed parameters to balance the signal distribution, ensuring that pixels in the notch region receive appropriate signals to achieve uniform display quality matching the non-notch areas.
2Manufacturing precision
If capacitance compensation structures are added to compensate for loading capacitance differences, then display uniformity is improved, but the device complexity increases
Solution Approach 1:
The capacitance compensation function is merged with the existing gate line structure. The first and second gate lines serve dual purposes: they function as signal transmission lines and simultaneously provide capacitance compensation for pixels in the notch region. This integration eliminates the need for separate compensation structures, maintaining simplicity while achieving display uniformity.
Solution Approach 2:
The gate lines are designed to perform multiple functions: signal transmission to pixels and capacitance compensation for pixels in the notch region. This multi-functionality reduces the overall device complexity by eliminating dedicated compensation structures while still achieving the desired display uniformity.
3Area of stationary object
If the capacitance compensation region is minimized to reduce border size, then the display area is improved, but the space for compensation structures is reduced
Solution Approach 1:
The gate lines extend into the notch region from both sides, utilizing the vertical space within the notch area rather than requiring additional horizontal border space. This dimensional approach allows capacitance compensation to be implemented within the existing display area, maximizing the usable display region while providing sufficient space for compensation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for loading capacitance, reducing border size and improving display uniformity by minimizing space occupation while enhancing the display effect.
Implementation Method 1
the second gate line forms a capacitor together with the second metal structure and the semiconductor structure
Data Source
AI summary
Provided is a display substrate, including a capacitance compensation region which is provided with a first capacitance compensation unit. The first capacitance compensation unit includes a semiconductor structure, a first metal structure, and a second metal structure sequentially arranged on a base substrate. An insulation layer between the semiconductor structure and the second metal structure is provided with a plurality of first via holes that are arranged along a first direction, and the second metal structure is connected to the semiconductor structure by means of the plurality of first via holes. The first metal structure includes a plurality of second gate lines extending along the first direction. In a second direction perpendicular to the first direction, a distance between two adjacent first via holes is at least greater than a sum of widths of two second gate lines.