Display Substrate Layout Using Poly-Silicon and Oxide TFTs
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Solution Overview
Problem
Existing display technologies face challenges in achieving high resolution and high transmittance simultaneously, particularly in flexible displays using OLEDs or QLEDs, due to limitations in pixel layout and signal line configurations.
Innovation Solution
The display substrate design includes symmetrical arrangements of sub-pixels along signal lines, integrated power supply connections, and specific transistor configurations to optimize pixel layout and reduce bezel size, incorporating poly silicon and oxide transistors to enhance resolution and transmittance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional pixel layout and signal line configurations are used, then device complexity is reduced, but resolution and transmittance cannot be simultaneously improved
Solution Approach 1:
The patent employs asymmetrical pixel layout where even-numbered rows and odd-numbered rows are arranged differently relative to signal lines. Specifically, even rows are positioned on one side of the scan signal line while odd rows are positioned on the other side, creating an asymmetrical pattern that optimizes both resolution and transmittance without requiring complex symmetric configurations
Solution Approach 2:
The patent utilizes dimensional optimization by arranging pixels at different distances from signal lines in alternating rows. This creates a multi-dimensional layout pattern where pixel positions are optimized in both horizontal and vertical dimensions, achieving high resolution while maintaining signal transmission efficiency
2Manufacturing precision
If more signal lines and transistors are added to improve resolution, then manufacturing precision increases, but device complexity and power consumption increase
Solution Approach 1:
The patent implements multi-functional transistors that serve multiple purposes. The reset transistor not only resets the pixel but also functions in compensation circuits, while the drive transistor manages both data writing and light emission control. This multi-functionality reduces the total transistor count while maintaining high pixel definition
Solution Approach 2:
The patent combines multiple signal line functions into fewer lines. The scan signal line serves both as a control line for pixel switching and as part of the compensation mechanism. Power supply lines are integrated to serve multiple pixel rows simultaneously, reducing overall device complexity while achieving precise pixel control
3Use of energy by moving object
If signal line width is increased to reduce resistance, then power consumption decreases, but transmittance and resolution are compromised
Solution Approach 1:
The patent applies different line width specifications to different signal lines based on their specific functional requirements. Power supply lines have larger widths to minimize resistance and power loss, while scan signal lines and data lines have optimized widths that balance transmittance and electrical performance. This localized optimization achieves low power consumption without compromising overall transmittance
Solution Approach 2:
The patent optimizes signal line parameters including width, thickness, and material composition to achieve the best balance between resistance and transmittance. By changing these parameters locally in different regions of the display, the patent reduces power consumption in high-current areas while maintaining high transmittance in pixel-dense regions
4Manufacturing precision
If pixel density is increased to improve resolution, then manufacturing precision increases, but bezel size and device area increase
Solution Approach 1:
The patent segments the display area into optimized pixel regions and signal line regions. By carefully segmenting the layout to place pixels at optimal distances from signal lines and organizing pixels in efficient patterns, the patent maximizes the active display area while minimizing bezel requirements for a given resolution
Data Source
AI summary
A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.