Display Transistor Substrate Wiring Layout for Lower Parasitic Loading
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Solution Overview
Problem
The existing techniques for laying out a large number of signal lines in display devices using multiple wiring layers with insulating films in between result in increased parasitic resistance and capacitance, leading to performance issues such as streaks and inefficient use of the frame region due to resistance differences between layers.
Innovation Solution
A transistor substrate with a configuration that includes signal lines formed in two distinct layers, where the first signal line is connected to a driving driver and passes through the second layer in the edge region, and UV-curable resin is used in the edge region to create gaps for ultraviolet light irradiation, allowing for efficient wiring layout while minimizing the impact on display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If signal lines are distributed to multiple wiring layers with insulating films, then the number of signal lines can be increased, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent transitions from planar wiring layout to three-dimensional stacked wiring layers, allowing signal lines to be routed in multiple layers vertically stacked with insulating films. This dimensional change enables increased signal line capacity while managing parasitic effects through proper layer spacing and insulation design.
Solution Approach 2:
Insulating films are introduced as intermediary layers between adjacent wiring layers. These insulating films act as mediators that electrically isolate the signal lines in different layers, preventing unwanted coupling and reducing parasitic capacitance between layers while allowing compact vertical stacking.
2Productivity
If lead-out lines are concentrated in the frame region, then wiring density increases, but resistance differences cause streaks
Solution Approach 1:
The patent applies different wiring configurations to different regions: in the frame region, multiple wiring layers are used with specific routing patterns, while in the display region, the wiring structure adapts to pixel requirements. This local differentiation allows efficient lead-out line concentration in the frame region while maintaining resistance uniformity through region-specific optimization.
Solution Approach 2:
By utilizing multiple vertical wiring layers, the patent distributes lead-out lines across different height levels rather than concentrating them in a single planar layer. This vertical distribution reduces planar density while maintaining electrical connectivity, and allows for more uniform current distribution that minimizes resistance variations and streak artifacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic resistance and capacitance, balances signal line resistance, and narrows the frame region, thereby improving the display device's performance and image quality by optimizing the layout of signal lines.
Implementation Method 1
UV-curable resin is used in the edge region to create gaps for ultraviolet light irradiation
Data Source
AI summary
In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.