Display Substrate Pin Layout for Aging Space in Bonding Areas

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Solution Overview

Problem

The increasing number of circuit boards and bonding pins in display products with improved resolution and Flexible Multi-Layer On cell structure has resulted in insufficient space for arranging aging pins in the bonding area, necessitating a more efficient pin arrangement to facilitate effective testing and bonding.

Innovation Solution

The display substrate design includes alternating aging pin groups between bonding pin groups, with specific configurations for transmitting gate drive control and direct current signals, ensuring adequate space and connectivity for aging pins, and optimizing signal consistency through side-by-side arrangement of aging and bonding pin groups.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the number of circuit boards and bonding pins is increased to improve display resolution and structure, then the display quality and functionality are improved, but the space for arranging aging pins in the bonding area becomes insufficient

Engineering Contradiction:
Improvedisplay resolutionVSAvoidbonding area space
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The bonding area is segmented into multiple bonding pin groups arranged along the first direction, with aging pin groups positioned between adjacent bonding pin groups. This segmentation allows the limited bonding area to accommodate both bonding pins and aging pins by dividing the space into functional zones, thereby resolving the space insufficiency problem while maintaining high display resolution requirements.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If aging pins are arranged in the bonding area to enable testing, then the testing capability is improved, but the bonding pin arrangement and space utilization become more complex

Engineering Contradiction:
Improvetesting capabilityVSAvoidpin arrangement complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

Aging pin groups are locally positioned in specific regions between bonding pin groups along the first direction, rather than uniformly distributing all pins throughout the bonding area. This localized arrangement provides testing capability where needed while maintaining a simple and systematic overall pin arrangement structure, avoiding excessive complexity in the bonding area design.

Inventive Principle:
Principle #3Local quality

3Reliability

If multiple aging pin groups are arranged between bonding pin groups, then the signal transmission for aging and testing is improved, but the bonding pin group arrangement becomes more complex

Engineering Contradiction:
Improvesignal consistencyVSAvoidpin group arrangement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple aging pin groups are arranged along the first direction (horizontal dimension) between bonding pin groups, utilizing the spatial dimension to accommodate multiple aging pin groups without increasing vertical complexity. This dimensional arrangement ensures adequate signal transmission paths for aging and testing while maintaining a systematic and manageable pin group structure through ordered positioning.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250359443A1Display substrate and display apparatus
Publication Date: 2025.11.20 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US20250359443A1 patent drawing
  • US20250359443A1 patent drawing
  • US20250359443A1 patent drawing

AI summary

A display substrate, including: a base substrate, multiple sub-pixels, multiple data lines, multiple test circuit groups, multiple aging pin groups and multiple binding pin groups. The base substrate includes a display area and a binding area. The multiple sub-pixels are in the display area. The multiple data lines are electrically connected to the multiple sub-pixels. The multiple test circuit groups are arranged along a first direction and electrically connected to the multiple data lines. The multiple aging pin groups and the multiple binding pin groups are in the binding area and on a side of the multiple test circuit groups facing away from the display area. The multiple binding pin groups are arranged along the first direction, and at least one aging pin group is arranged between every two adjacent binding pin groups. Each binding pin group is configured to be bonded and connected to at least one circuit board.