Display Substrate Pixel Layout for High Resolution and Transmittance
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Solution Overview
Problem
Existing display configurations face challenges in achieving high resolution and high transmittance simultaneously, making it difficult to meet the increasing demands for finer screens and requirements such as under-display fingerprint and camera functionality.
Innovation Solution
The display substrate is designed with a specific layer structure including poly silicon transistors, oxide transistors, and conductive layers, where sub-pixels are arranged in symmetrical patterns to optimize pixel layout and reduce metallic line areas, enhancing transmittance and resolution by integrating power supply lines and data signal lines in a way that minimizes bezels and increases non-metallic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional pixel layout is used, then device complexity is manageable, but resolution and transmittance cannot be simultaneously optimized
Solution Approach 1:
The patent applies asymmetry by making adjacent rows of sub-pixels asymmetrical in conventional designs, but the invention reverses this by making them symmetrical. This symmetrical arrangement allows for more efficient space utilization and reduces the number of different signal line configurations needed, thereby improving resolution without proportionally increasing device complexity
Solution Approach 2:
The scan signal line is designed to serve multiple functions: it acts as a gate electrode for poly silicon transistors in one region and as a control signal line for oxide transistors in another region. This multi-functionality reduces the need for separate signal lines, optimizing pixel layout space and improving resolution without linearly increasing device complexity
2Manufacturing precision
If more signal lines are added to improve resolution, then manufacturing precision improves, but transmittance decreases due to increased metallic line areas
Solution Approach 1:
The scan signal line serves dual purposes: controlling poly silicon transistors and oxide transistors. By making the signal line multi-functional, the patent reduces the total number of separate metallic lines needed, thereby maintaining high resolution while increasing the non-metallic line area ratio to improve transmittance
Solution Approach 2:
The patent merges the control functions for different transistor types into a single scan signal line structure. This consolidation reduces redundant metallic lines in the pixel layout, increasing the proportion of non-metallic areas and thus improving light transmittance while preserving resolution
3Area of stationary object
If symmetrical sub-pixel arrangement is implemented, then pixel layout space is reduced and transmittance improves, but device complexity increases due to integrated conductive layers
Solution Approach 1:
The patent utilizes vertical stacking of multiple conductive layers to achieve functional integration. By arranging conductive elements in different vertical dimensions rather than spreading them horizontally, the pixel layout space is reduced while the complexity is managed through layered organization rather than planar complexity
4Area of stationary object
If integrated conductive layers are used to reduce pixel space, then area decreases and transmittance improves, but manufacturing complexity increases
Solution Approach 1:
The conductive structure is segmented into distinct layers: a first conductive layer for poly silicon transistor control and a second conductive layer for oxide transistor control. This segmentation allows each layer to be optimized independently for its specific function while achieving overall integration, reducing manufacturing complexity compared to a fully integrated single-layer approach
Data Source
AI summary
A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.