Display Substrate Alternating Polarity Signal Testing
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Solution Overview
Problem
Existing display substrates face challenges in effectively detecting shorts between pixels due to data signals of the same polarity, which prevents accurate defect detection.
Innovation Solution
The display substrate incorporates a configuration with alternating polarities of data signals on adjacent sub-pixels and the use of test gate clocks to identify reference voltages, allowing for effective detection of shorts between pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data signals having the same polarities are charged to adjacent sub-pixels, then the display substrate can be manufactured with simpler signal generation, but the defect detection capability deteriorates because shorts between pixels cannot be effectively detected
Solution Approach 1:
The patent applies preliminary action by configuring the display substrate with alternating polarity data signals before actual operation. Test pads and gate lines are pre-configured to apply opposite polarities to adjacent sub-pixels, enabling defect detection capability to be built into the manufacturing stage. This allows detection of shorts between pixels before the display enters normal operation with uniform polarity signals.
Solution Approach 2:
The patent changes the polarity parameter of data signals applied to adjacent sub-pixels. Instead of using the same polarity for all sub-pixels, the invention alternates polarities between adjacent sub-pixels during test operations. This parameter change enables voltage differences to manifest at test pads when shorts occur, making defects detectable through voltage measurements.
2Measurement precision
If data signals having different polarities are charged to adjacent sub-pixels, then the defect detection capability is improved by enabling effective detection of shorts between pixels, but the device complexity increases due to additional signal inversion requirements
Solution Approach 1:
The patent applies universality by making the gate lines serve multiple functions. The same gate lines that control pixel operation during normal display function are also used to apply alternating polarity test signals for defect detection. The test pads similarly serve dual purposes: they are part of the normal pixel structure during operation and function as voltage sensing points during defect detection. This multi-functionality reduces the need for separate dedicated test structures.
Solution Approach 2:
The patent uses test pads as intermediaries to detect shorts between pixels. Instead of directly measuring conditions within the pixel structure, the invention introduces test pads that act as intermediary sensing points. These test pads receive voltage signals from sub-pixels through the pixel structure and transmit detection information to external testing equipment, simplifying the detection mechanism while maintaining high measurement precision.
3Measurement precision
If a test pad outputs gate clocks to adjacent gate lines, then the defect detection ratio is improved by enabling voltage comparison across pixels, but the time required for comprehensive testing increases
Solution Approach 1:
The patent applies periodic action by using alternating gate clock signals with different polarities that are sequentially applied to adjacent gate lines. Instead of continuously testing all pixels simultaneously, the invention periodically switches between applying positive and negative gate clocks to different gate lines, allowing systematic testing of pixel pairs. This periodic testing approach enables comprehensive defect detection while managing testing time through structured signal application sequences.
Data Source
AI summary
A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.