Display Substrate Power-Line Layout for Uniform 8K OLED Driving
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Solution Overview
Problem
High-resolution OLED displays face issues such as increased pixel density, signal line resistance-capacitance load, and parasitic resistance and capacitance, leading to signal delay, voltage drop, and non-uniform display, particularly in large 8K resolution devices.
Innovation Solution
The display substrate incorporates auxiliary electrode lines connected in parallel with power lines to reduce resistance, and signal lines are arranged to avoid direct adjacency, reducing parasitic capacitance and signal delay, thereby improving display uniformity and reducing color shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel density is increased to achieve high-resolution display, then display resolution is improved, but signal line resistance-capacitance load increases causing signal delay and voltage drop
Solution Approach 1:
The power supply line is divided into multiple segments with different voltage levels (first power supply voltage and second power supply voltage) to reduce the voltage drop along the signal line. This segmentation allows different regions of the display panel to receive appropriate voltage levels, compensating for the increased resistance-capacitance load caused by higher pixel density.
Solution Approach 2:
Different regions of the display panel are provided with different power supply voltages according to their specific needs. The first power supply voltage is applied to regions farther from the drive circuit where voltage drop is more significant, while the second power supply voltage is applied to regions closer to the drive circuit. This local quality approach ensures optimal signal transmission quality across the entire high-resolution display.
2Reliability
If signal lines are arranged to reduce parasitic capacitance, then signal delay is reduced, but device complexity increases
Solution Approach 1:
The display panel is divided into multiple regions with different power supply voltage assignments. By segmenting the power supply network into first and second power supply lines serving different regions, the patent reduces parasitic capacitance effects in signal transmission paths without requiring complete redesign of the entire signal line arrangement.
Solution Approach 2:
The patent introduces a new dimension of voltage level differentiation (first power supply voltage and second power supply voltage) to solve the signal transmission problem. Instead of only adjusting the physical arrangement of signal lines in two dimensions, the solution adds a voltage level dimension, allowing multiple voltage levels to coexist and reduce parasitic capacitance effects.
3Reliability
If power lines are designed to reduce resistance, then voltage drop is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent changes the voltage level parameter by introducing two different power supply voltages (first and second power supply voltages) instead of using a single voltage level. This parameter change allows the system to operate at optimized voltage levels for different regions, reducing voltage drop while managing parasitic capacitance effects through voltage differentiation rather than solely through geometric optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively alleviates voltage drops and rises, enhancing display quality by minimizing resistance-capacitance loads and maintaining uniform power distribution across sub-pixels, thus improving display uniformity and reducing color shift.
Implementation Method 1
a liquid crystal module including a first substrate, a second substrate, a liquid crystal composition disposed between the first substrate and the second substrate
Data Source
Figure 1A~1B
Figure 1C~1E
Figure 2A
AI summary
A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array, and the column direction is a first direction and the row direction is a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region which are successively arranged in the first direction and are electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole, and the first via hole region is shifted in the second direction with respect to the body region, so that the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction. The display substrate can effectively improve the display effect.