Display Substrate Layout for Short TFT Active Layer Protrusions
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Solution Overview
Problem
The existing semi-exposure (SDT) process for manufacturing thin film transistors leads to long active layer protrusions at the edge of source-drain metal layers, causing increased parasitic capacitance, signal transmission delays, line image retention, and instability due to varying light exposure conditions, affecting the performance and reliability of liquid crystal display devices.
Innovation Solution
A display substrate design with a semiconductor layer and conductive layer configuration, where the semiconductor layer includes a channel region and doped region pattern, and the conductive layer has a data line and electrodes with strategically positioned protrusions, optimized to reduce the size of these protrusions to less than 3 microns, ensuring proper alignment and minimizing the impact of backlight exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the active semiconductor layer and source-drain metal layer are semi-exposed by the same mask to form TFT, then the tact time is improved, but the active layer protrusion at the edge of source-drain metal layer becomes long
Solution Approach 1:
The patent divides the mask structure into two separate masks: a first mask for exposing the active semiconductor layer and a second mask for exposing the source-drain metal layer. This segmentation allows independent control of exposure dimensions, enabling the active layer width to be precisely controlled while minimizing edge protrusions, thereby resolving the contradiction between improved productivity and reduced protrusion length.
Solution Approach 2:
The patent applies different exposure characteristics to different regions by using masks with specifically designed patterns. The first mask creates a precise active layer region, while the second mask creates the source-drain metal layer with controlled edge alignment. This local quality control ensures that the active layer protrusion is minimized at critical edges while maintaining overall manufacturing efficiency.
2Quantity of substance
If the active layer protrusion is long, then the parasitic capacitance increases, but the signal transmission delay and image retention issues worsen
Solution Approach 1:
The patent extracts and eliminates the harmful active layer protrusion at the edge of the source-drain metal layer by using a two-mask exposure process. By separately controlling the exposure of the active layer and source-drain metal layer, the protrusion that causes parasitic capacitance is removed, thereby improving signal transmission stability and reducing image retention issues.
Solution Approach 2:
The patent applies preliminary anti-action by designing the mask patterns to prevent the formation of excessive active layer protrusion before it occurs. The first mask defines the active layer boundaries, and the second mask aligns the source-drain metal layer to minimize overlap and protrusion, thereby preemptively preventing parasitic capacitance formation and signal transmission problems.
3Reliability
If the protrusion size is reduced to less than 3 microns, then the display issues like water ripples and image retention are minimized, but the manufacturing precision requirement increases
Solution Approach 1:
The patent segments the exposure process into two distinct steps with separate masks, allowing precise control of the active layer and source-drain metal layer independently. This segmentation enables the protrusion size to be controlled within 3 microns by optimizing each mask's exposure parameters separately, thereby achieving both display stability and manageable manufacturing precision.
Solution Approach 2:
The patent utilizes parameter changes in the exposure process, such as adjusting exposure time, energy, and mask patterns, to precisely control the active layer protrusion size. By optimizing these parameters for each mask step, the protrusion is reduced to less than 3 microns, minimizing display issues while maintaining feasible manufacturing precision requirements.
Data Source
AI summary
A display substrate, manufacturing method thereof, and a display device. The display substrate includes a base substrate and a semiconductor layer and a conductive layer on the base substrate. The semiconductor layer includes a channel region and a doped region pattern of a transistor; the conductive layer includes a data line, and a first electrode and a second electrode of the transistor. An extension direction of an overlapping portion of the semiconductor layer with the data line is the same as an extension direction of the data line, and the semiconductor layer includes a first protrusion portion, and a size of an interval between an edge of the first protrusion portion away from the data line and the edge of the data line is greater than 0 and smaller than 3.0 microns.