Display Substrate Pixel Circuit Layout for Lower RC Signal Delay
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Solution Overview
Problem
In OLED display technology, high-resolution products require improved structural design of display substrates to manage increased pixel density, leading to signal line resistance-capacitance load issues, causing signal delay, voltage drop, and display quality degradation due to increased parasitic capacitance and overlap of signal lines.
Innovation Solution
The display substrate is designed with a pixel circuit arrangement that includes a drive sub-circuit, data write sub-circuit, compensation sub-circuit, and storage sub-circuit, with specific terminal configurations and interconnections to manage signal lines and power distribution, and a mesh-shaped power line structure to reduce resistance and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to achieve high-resolution display, then display resolution is improved, but signal line resistance-capacitance load increases causing signal delay and voltage drop
Solution Approach 1:
The pixel circuit is divided into multiple functional sub-circuits (drive sub-circuit, data write sub-circuit, compensation sub-circuit, storage sub-circuit) that are distributed in a grid pattern. This segmentation allows signal lines to be shorter and more localized, reducing RC load while maintaining high pixel density for high-resolution display.
Solution Approach 2:
The sub-circuits are arranged in a two-dimensional grid pattern (multiple columns in first direction and multiple rows in second direction) rather than linear arrangement. This spatial distribution in multiple dimensions reduces the length of signal lines and minimizes parasitic capacitance overlap, thereby reducing signal delay and voltage drop while achieving high pixel density.
2Area of stationary object
If signal lines are extended to cover larger display areas, then display area is increased, but parasitic capacitance and signal delay increase
Solution Approach 1:
The display is segmented into multiple small sub-circuits distributed across the display area, each handling local pixel control. This eliminates the need for long extended signal lines across the entire display area, as each sub-circuit receives signals locally, thereby reducing signal delay while maintaining large display area coverage.
Solution Approach 2:
By distributing sub-circuits in a two-dimensional grid pattern across the display area, the patent creates multiple local signal distribution points. This dimensional arrangement allows signals to be routed to nearby sub-circuits rather than traveling across the entire display area, reducing signal delay while covering large areas.
3Power
If power lines are added to provide sufficient power voltage, then power distribution capability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple power lines into a mesh-shaped power line structure where power lines in the first direction and power lines in the second direction intersect and connect. This merging approach provides redundant power paths and ensures sufficient power voltage delivery to all sub-circuits while maintaining a systematic and organized structure rather than adding complex individual connections.
Solution Approach 2:
The power distribution system is extended from one-dimensional linear power lines to a two-dimensional mesh structure with power lines running in both first and second directions. This dimensional expansion creates multiple power delivery paths across the display substrate, ensuring adequate power voltage reaches all distributed sub-circuits while maintaining structural regularity.
Data Source
AI summary
A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel and a second sub-pixel which are directly adjacent in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other.