Display Substrate Reset Signal Line Design for GOA Loading Balance
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Solution Overview
Problem
The integration of dummy pixel rows in display panels leads to an imbalance in Gate driver On Array (GOA) signal loading, resulting in differences in charging times between regions with and without dummy pixel lines, which affects display quality.
Innovation Solution
A display substrate design where the first and second reset transistors in each sub-pixel are controlled by the same reset signal line, ensuring consistent GOA loading across all regions, including those with and without dummy pixel lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If dummy pixel rows are integrated into the display panel, then the display area is increased and structural flexibility is improved, but GOA signal loading becomes unbalanced and charging times differ between regions
Solution Approach 1:
The patent applies local quality by differentiating the reset signal line connections between normal pixel rows and dummy pixel rows. Normal pixel rows use cascade-connected reset signal lines where each row's reset line is connected to the previous row, while dummy pixel rows use independent reset signal lines directly connected to the GOA. This localized differentiation ensures that dummy pixel rows do not add extra loading to the cascade signal path, maintaining uniform charging times across all regions while preserving the benefits of dummy pixel integration.
2Adaptability or versatility
If dummy pixel rows are added to the display panel, then the overall display structure is enhanced, but differences in GOA loading between regions with and without dummy pixel lines occur
Solution Approach 1:
The patent implements local quality by creating distinct reset signal line configurations for different regions: dummy pixel rows have independent reset lines connected directly to the GOA, while normal pixel rows use cascade-connected reset lines. This regional differentiation allows the display structure to accommodate dummy pixel rows for enhanced flexibility and adaptability, while simultaneously maintaining stable and consistent GOA loading characteristics across all regions by preventing dummy rows from introducing variable loading into the cascade path.
3Device complexity
If the same reset signal line controls both first and second reset transistors in each sub-pixel, then device complexity is reduced, but precise control of different transistor operations may be compromised
Solution Approach 1:
The patent applies periodic action by utilizing the timing characteristics of the reset signal to sequentially control the first and second reset transistors. The reset signal is applied in specific time periods: during the initialization phase, the first reset transistor is activated to reset the gate of the drive transistor, and during the emission control phase, the second reset transistor is activated to reset the light emitting device. This time-division control approach maintains a simple single-signal-line structure while achieving precise control over different transistor operations at different time periods.
Data Source
AI summary
A display substrate includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes an initial signal line, a reset signal line, a scan signal line and multiple transistors. Multiple transistors include a drive transistor, a data writing transistor, a first reset transistor and a second reset transistor. The first reset transistor resets a gate of the drive transistor under control of the reset signal line. The display substrate further comprises dummy pixel rows among the plurality of sub-pixels, at least one row of the plurality of sub-pixels is arranged adjacent to a dummy pixel row, the dummy pixel row comprises a plurality of dummy sub-pixels, a dummy sub-pixel comprises a dummy pixel drive circuit.