Display Substrate Scan-Driver Layout for Dense Peripheral Wiring
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Solution Overview
Problem
Existing display substrates face challenges in layout design due to limited space for signal lines and power lines, particularly with dense wirings, which complicates the integration of gate driving circuits and increases the occupied space, especially in large-size display panels.
Innovation Solution
The display substrate incorporates a first scan driving circuit with cascaded shift registers, power lines, and signal lines arranged to minimize space usage, with trigger signal lines positioned away from the pixel array region, and power lines strategically overlapped to optimize layout and facilitate signal introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If signal lines and power lines are arranged in dense wirings to integrate gate driving circuits, then the driving capability is improved, but the occupied space increases and layout design becomes complicated
Solution Approach 1:
The patent utilizes multi-layer wiring structures to arrange signal lines and power lines in different vertical layers, transforming a two-dimensional layout problem into a three-dimensional spatial arrangement. This allows dense wirings to be achieved without proportionally increasing the planar occupied space, as lines that would otherwise need to be laid out side-by-side in the same plane are instead stacked in different layers, effectively reducing the footprint while maintaining the required wiring density for driving capability.
Solution Approach 2:
The gate driving circuit is divided into multiple independent modules or units that can be separately designed and arranged. By segmenting the circuit into functional blocks (such as shift register units, storage units, and output units), the layout can be optimized to minimize space occupation while maintaining proper signal routing. Each segment can be independently positioned to reduce overall complexity and occupied area.
2Ease of manufacture
If trigger signal lines are positioned away from the pixel array region to optimize layout, then the layout efficiency is improved, but the signal line length increases
Solution Approach 1:
Trigger signal lines are routed through different vertical layers to reach the gate driving circuit. Instead of extending long horizontal paths across the pixel array region, the signal lines can descend vertically through intermediate layers to access the driving circuit located in the peripheral region. This three-dimensional routing approach maintains layout efficiency by keeping the overall signal path compact while avoiding long lateral extensions that would increase line length and parasitic effects.
3Area of stationary object
If power lines are strategically overlapped to optimize layout, then the space usage is reduced, but the wiring complexity increases
Solution Approach 1:
Power lines are arranged in overlapping configurations across different vertical layers, creating a compact three-dimensional power distribution network. This multi-layer overlapping approach allows power delivery to be achieved with minimal planar space occupation, as power lines in different layers can share the same lateral footprint. The wiring complexity is managed through systematic layer assignment and routing rules that organize the overlapping structures in a predictable manner.
Data Source
AI summary
A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.