Display Substrate Scanning Line Layering for RC Delay Reduction
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Solution Overview
Problem
In large-size, high-resolution OLED display devices, there is limited space for pixel arrangement, and the resistance capacitance (RC) delay of signal lines is excessive due to line width and spacing, affecting display performance.
Innovation Solution
A display substrate with a base substrate and pixel units, each comprising sub-pixels with driving circuitry and light-emitting elements, and a light shielding layer between the driving circuitry and the base substrate. The scanning lines are thick (0.5 μm to 1.5 μm) and arranged at the same layer as the light shielding layer, reducing resistance and load, and preventing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the line width and line spacing of scanning lines are reduced to fit more pixels in large-size displays, then the pixel density is improved, but the resistance capacitance (RC) delay of signal lines increases excessively
Solution Approach 1:
The patent introduces a new spatial dimension by placing the scanning line and light shielding layer at the same layer level (second conductive layer), rather than stacking them vertically. This lateral arrangement allows the scanning line to extend further in the first direction without increasing vertical capacitance, thereby reducing RC delay while maintaining high pixel density through optimized line spacing and width in the planar dimension.
Solution Approach 2:
The patent applies different thicknesses to different portions of the scanning line. The scanning line has a first thickness in regions where it needs to minimize capacitance (reducing RC delay) and a second, greater thickness in other regions to maintain signal integrity. This local variation in geometric properties allows optimization of electrical characteristics without compromising overall display performance.
2Reliability
If the scanning line thickness is increased to reduce resistance and load, then the signal transmission quality is improved, but the occupation of space and potential interference with other components increases
Solution Approach 1:
By arranging the scanning line and light shielding layer at the same layer level rather than stacking them vertically, the patent utilizes lateral space more efficiently. This allows the scanning line to have sufficient thickness for low resistance while avoiding vertical space conflicts with other conductive layers, effectively decoupling the thickness requirement from vertical space occupation.
Solution Approach 2:
The scanning line is divided into multiple segments with different thicknesses along its extension direction. This segmentation allows each portion to be optimized independently - thinner sections reduce capacitance and resistance, while thicker sections provide necessary signal integrity, all within the same planar footprint without requiring additional vertical space.
Data Source
AI summary
A display substrate and a display device. The display substrate includes a base substrate, and a plurality of pixel units and a plurality of scanning lines on the base substrate. Each pixel unit includes a plurality of sub-pixels and a light shielding layer, the plurality of sub-pixels is arranged in sequence in a first direction, each sub-pixel includes a sub-pixel driving circuitry and a light-emitting element coupled to each other, and the sub-pixel driving circuitry is configured to provide a driving signal to the light-emitting element. At least a part of the light shielding layer is arranged between the sub-pixel driving circuitry and the base substrate. Each scanning line includes at least a part extending in the first direction, is coupled to a corresponding sub-pixel driving circuitry, and is arranged at a same layer as the light shielding layer.