Display Substrate Layout with Shared Gate Vias for Ultra-High PPI
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Solution Overview
Problem
Existing silicon-based OLED displays face challenges in achieving ultra-high pixels per inch (PPI) due to limitations in design and layout of transistors and signal lines, which hinder the improvement of display quality and resolution.
Innovation Solution
The display substrate design incorporates a novel layout with integrated gate electrodes and shared via holes in a gap region, along with symmetrical transistors and shared electrodes, maximizing PPI by optimizing the arrangement of transistors and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional transistor and signal line layout is used, then manufacturing is simpler, but pixels per inch (PPI) is limited and cannot achieve ultra-high resolution
Solution Approach 1:
The patent merges multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) into a shared gate electrode structure. This integration reduces the number of separate components while maintaining the functionality of controlling multiple transistors, thereby increasing pixel density without proportionally increasing layout complexity
Solution Approach 2:
The shared gate electrode serves multiple functions by simultaneously controlling the first transistor, second transistor, and third transistor. This multi-functional design allows a single structure to perform what previously required multiple separate gate electrodes, enabling higher PPI
2Manufacturing precision
If more transistors and signal lines are added to increase PPI, then display resolution improves, but the area occupied by each pixel increases
Solution Approach 1:
Multiple transistor gate electrodes are merged into a shared gate electrode structure, reducing the total area required for gate electrodes within each pixel. This consolidation allows more pixels to be packed into the same display area, increasing PPI without increasing overall pixel area
Solution Approach 2:
The patent extends signal lines (first scan signal line, second scan signal line) into the gap region between pixel regions, utilizing vertical space rather than horizontal space. This dimensional approach allows signal routing without increasing the horizontal pixel footprint, enabling higher pixel density
3Ease of manufacture
If gate via holes are distributed across different regions, then transistor control is simpler, but the number of via holes increases and manufacturing complexity increases
Solution Approach 1:
Multiple gate via holes that would traditionally be distributed across different regions are merged and concentrated into a single gap region. This consolidation reduces the total number of via hole locations that need to be managed and fabricated, simplifying the manufacturing process while reducing structural complexity
Solution Approach 2:
The gap region serves as an intermediary space that hosts all the gate via holes. This intermediary region acts as a centralized hub for connecting scan signal lines to gate electrodes, organizing the via holes in a manageable location that simplifies both design and manufacturing
Data Source
AI summary
A display substrate, a manufacturing method thereof and a display apparatus are provided. The display substrate includes multiple sub-pixels, a sub-pixel includes a first region (q1), a gap region (q3) and a second region (q2); the sub-pixel includes a first transistor (T1) including first active layer (1) and first gate electrode (11), a second transistor (T2) including second active layer (2) and second gate electrode (12) and a third transistor (T3) including third active layer (3) and third gate electrode (13); the first active layer is disposed in the first region, the second active layer and the third active layer are disposed in the second region, and via holes through which the first gate electrode and the third gate electrode are connected to a scan signal line and a via hole through which the second gate electrode is connected to the first transistor are provided in the gap region.