Display Substrate Shielding Layer Reduces Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In OLED display devices, parasitic capacitance between the gate electrode and data line causes voltage deviations, leading to display errors and vertical crosstalk due to rapid changes in data signals, affecting the light-emitting effect and display accuracy.
Innovation Solution
A display substrate with a pixel driving circuit that includes a driving transistor and a gate leading line electrically connected to the gate electrode, where the gate leading line is positioned between the gate electrode and the base substrate, and a shielding layer is used to prevent parasitic capacitance by being insulated and overlapped with the gate electrode in a direction perpendicular to the base substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate electrode and data line are positioned close to each other for compact circuit design, then device integration is improved, but parasitic capacitance increases causing voltage deviations and display errors
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the gate electrode and data line. This shielding layer acts as a mediator that blocks the harmful electromagnetic coupling between the two conductors, reducing parasitic capacitance while allowing the gate leading line to pass through. The shielding layer is electrically connected to the common potential, creating a Faraday cage effect that isolates the gate electrode from the data line's electromagnetic field.
Solution Approach 2:
The solution transitions from a planar two-dimensional layout to a three-dimensional stacked structure. The gate leading line is positioned in a different layer (between the gate electrode and base substrate) rather than in the same plane as the data line. This vertical separation in the third dimension reduces the overlapping area and electromagnetic coupling between the gate electrode and data line, thereby reducing parasitic capacitance while maintaining compact integration.
2Reliability
If the gate leading line is extended to connect the gate electrode to external circuits, then electrical connectivity is improved, but the leading line overlaps with the data line increasing parasitic capacitance
Solution Approach 1:
The gate leading line is routed through a different spatial layer (vertical dimension) rather than overlapping in the same plane with the data line. By positioning the gate leading line between the gate electrode and base substrate in a stacked configuration, the patent eliminates planar overlap between the leading line and data line, reducing parasitic capacitance while maintaining electrical connectivity to external circuits.
3Speed
If rapid changes in data signals are allowed for high-speed display updates, then response speed is improved, but voltage deviations occur due to parasitic capacitance causing display errors
Solution Approach 1:
The shielding layer serves as a protective intermediary that blocks capacitive coupling between the data line and gate electrode. This allows rapid data signal transitions without inducing voltage deviations on the gate electrode, enabling high-speed display updates while maintaining display accuracy by preventing parasitic capacitance effects.
Data Source
AI summary
A display substrate and a manufacturing method thereof, and a display panel are disclosed. The display substrate includes a base substrate and a pixel driving circuit on the base substrate; and the pixel driving circuit includes a driving transistor and a gate leading line, the driving transistor includes a gate electrode, the gate leading line is electrically connected to the gate electrode, and the gate leading line is between the gate electrode and the base substrate.