Display Substrate Stacked Capacitor Layout for Signal Integrity
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Solution Overview
Problem
Micro OLED displays face challenges in achieving high resolution and efficient signal transmission due to increased parasitic capacitance and resistance in signal lines, leading to signal delay and voltage drop, which affect display quality.
Innovation Solution
The display substrate incorporates a optimized layout and wiring design, featuring a pixel circuit with a data writing sub-circuit, storage sub-circuit, and driving sub-circuit, including a resistance device to manage current flow and reduce parasitic effects, thereby improving signal integrity and display efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal lines are extended to cover larger display areas, then display area increases, but parasitic capacitance and resistance increase causing signal delay and voltage drop
Solution Approach 1:
The patent introduces a three-dimensional stacked capacitor structure where capacitor electrodes are arranged in vertical layers rather than only horizontal planes. This vertical stacking allows the capacitor to occupy additional dimensional space, increasing capacitance value without expanding the horizontal footprint of the pixel circuit, thereby maintaining compact pixel layouts needed for high-resolution displays while improving signal storage capability to compensate for transmission losses.
Solution Approach 2:
The patent integrates the storage capacitor structure with the pixel circuit layout by positioning capacitor electrodes adjacent to and overlapping with transistor regions. The first capacitor electrode is arranged adjacent to the first transistor, and the second capacitor electrode overlaps with the second transistor in the vertical direction. This merging approach maximizes space utilization within the pixel area, allowing efficient signal storage while maintaining compact circuit dimensions.
2Reliability
If pixel circuit components are increased to improve signal storage, then signal integrity improves, but pixel area increases reducing resolution
Solution Approach 1:
The patent transitions from planar capacitor geometry to a three-dimensional stacked configuration. The first capacitor electrode extends in the horizontal direction adjacent to the first transistor, while the second capacitor electrode is positioned above it in the vertical direction with overlapping projection. This vertical stacking multiplies the effective capacitance area without increasing the horizontal pixel footprint, enabling improved signal storage within constrained pixel dimensions.
Solution Approach 2:
The capacitor structure is nested within the pixel circuit layout by positioning electrodes to overlap with and adjacent to transistor regions. The second capacitor electrode is nested above the first capacitor electrode in the vertical direction, and both are integrated with the surrounding transistor structures. This nesting approach allows multiple functional elements to share the same horizontal space through vertical layering, maximizing component density.
Data Source
AI summary
A display substrate and a display device are provided. The display substrate includes a sub-pixel and the sub-pixel includes a pixel circuit including a data writing sub-circuit, a storage sub-circuit and a driving sub-circuit. The display substrate further includes a first connection electrode and the storage sub-circuit includes a storage capacitor; the first connection electrode is in a same layer as the second capacitor electrode and is insulated form the second capacitor electrode, and the second capacitor electrode electrically connects the first capacitor electrode to the data writing sub-circuit.