Display Substrate Internal Array Test Pins
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Solution Overview
Problem
The existing manufacturing process of display panels faces challenges in efficiently conducting array tests within the display substrate, as array test pins are typically external, leading to inconvenience and potential short circuits during removal.
Innovation Solution
The integration of array test pins within the display substrate allows for internal array testing, eliminating the need for external pins and simplifying the manufacturing process while preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If array test pins are located externally on the display substrate, then array testing can be performed, but the manufacturing process becomes complex and short circuits may occur during pin removal
Solution Approach 1:
The patent merges the array test pins with the display substrate by integrating them into the same glass substrate. The test pins are formed simultaneously with the display electrode patterns through the same ITO sputtering process, eliminating the need for separate external pins and their associated removal steps, thus simplifying manufacturing while maintaining testing reliability
Solution Approach 2:
The array test pins are prepared in advance during the same manufacturing process as the display electrode patterns. By forming the test pins and display electrodes simultaneously on the glass substrate before device assembly, the patent eliminates subsequent pin removal operations and prevents potential short circuits that could occur during removal
2Ease of manufacture
If array test pins are integrated within the display substrate, then manufacturing process is simplified and short circuit risk is reduced, but testing functionality must be maintained
Solution Approach 1:
The patent combines the array test pins with the display substrate structure, forming both the test pins and display electrode patterns simultaneously through ITO sputtering. This integration maintains full testing functionality while simplifying the manufacturing process by eliminating separate pin components and assembly steps
Solution Approach 2:
The ITO patterns on the glass substrate serve dual functions: as display electrode patterns for normal display operation and as array test pins for testing. This multi-functionality ensures that testing capability is preserved while the same structure simplifies manufacturing by eliminating dedicated external test pins
Data Source
AI summary
A display substrate and a display panel are disclosed. The display substrate includes a base substrate having an active area and a peripheral area surrounding the active area; a plurality of sub-pixels, in the active area; a plurality of first pins and a plurality of second pins located in the peripheral area; a plurality of first array test pins located between the plurality of first pins and the plurality of second pins and respectively electrically coupled to a plurality of array test signal lines; and a plurality of second array test pins located between the plurality of first pins and the plurality of second pins and extending in a direction along a boundary of the active area, wherein the plurality of first array test pins are located on at least one side of the plurality of second array test pins in the direction along the boundary of the active area.