Display Substrate Circuit Timing to Reduce LTPO Afterimages

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Solution Overview

Problem

Existing display technologies using Low Temperature Polycrystalline Oxide (LTPO) face issues with afterimages due to biased threshold voltage of drive transistors, leading to reduced display effectiveness.

Innovation Solution

A display substrate design with a circuit structure layer that includes pixel, scan, control, and buffer drive circuits, where reset signal lines are connected to either the buffer or scan/control drive circuits, ensuring a threshold time difference between signal transitions, and incorporating compensation transistors to mitigate threshold voltage biasing effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reset signal lines are connected to scan drive circuit or control drive circuit, then afterimages are reduced, but signal timing complexity increases

Engineering Contradiction:
Improveafterimage reductionVSAvoidsignal timing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by designing the circuit to ensure reset signals are activated before scan/control signals and maintain their effect afterward. The threshold time parameter t is calculated to ensure reset signals precede scan/control signals by sufficient margin, allowing threshold voltage recovery before normal operation begins, thus preventing afterimages while managing timing complexity through predefined parameters.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If threshold time is increased to allow transistor recovery, then display quality improves, but frame time consumption increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidframe time consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by introducing the threshold time parameter t as a design variable that balances recovery needs against frame time constraints. The formula t = K*(1/f)/N or t = K*(1/f)/(N+N0) allows optimization of reset duration based on refresh frequency f, number of rows N, and blank rows N0, ensuring adequate transistor recovery without excessive frame time consumption.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If compensation transistors are added to mitigate threshold voltage biasing, then display effectiveness improves, but circuit complexity increases

Engineering Contradiction:
Improvedisplay effectivenessVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies the intermediary principle by introducing compensation transistors as mediator elements that actively counteract threshold voltage biasing effects. These compensation transistors are strategically placed in the pixel circuit to balance the electrical characteristics and eliminate afterimages, improving display effectiveness while adding controlled circuit complexity through targeted compensation mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12394374B2Display substrate and display device
Publication Date: 2025.08.19 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12394374B2 patent drawing
  • US12394374B2 patent drawing
  • US12394374B2 patent drawing

AI summary

A display substrate and a display device are provided, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes a pixel circuit, a scan drive circuit, a control drive circuit and a buffer drive circuit; the pixel circuit includes a node reset transistor, a writing transistor, a reset signal line connected to a control electrode of the node reset transistor, a scan signal line connected to a control electrode of the writing transistor, and a control signal line; reset signal lines of pixel circuits of first to K-th rows are electrically connected with the buffer drive circuit, reset signal lines of pixel circuits of (K+1)-th to N-th row are electrically connected with the scan drive circuit or the control drive circuit.