Display Substrate Layout With Vertical Oxide TFT Electrodes
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Solution Overview
Problem
Current display technologies face challenges in achieving ultrahigh resolution due to short circuits between source and drain electrodes in metal oxide TFTs, which are exacerbated by the limitations of existing equipment and process routing, leading to instability and poor display performance.
Innovation Solution
The display substrate design separates low temperature poly-silicon and metal oxide thin film transistors into different layers, with source and drain electrodes positioned on opposite sides of the metal oxide semiconductor layer, and incorporates a light-shielding layer to prevent interference, while using independent via holes for connections to avoid short circuits and enhance stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the distance between source and drain electrodes is reduced to achieve higher resolution, then the resolution is improved, but short circuit between electrodes occurs
Solution Approach 1:
The patent transitions from a planar arrangement where source and drain electrodes are laterally separated to a vertical arrangement where they are separated along the thickness direction. The metal oxide semiconductor layer is positioned between the source electrode (on the first substrate) and the drain electrode (on the second substrate), achieving electrode separation through the third dimension while maintaining ultrahigh resolution.
Solution Approach 2:
The transistor structure is segmented into two separate substrates: the first substrate contains the source electrode and metal oxide semiconductor layer, while the second substrate contains the drain electrode. This segmentation allows independent optimization of each electrode's position and reduces the risk of short circuits while achieving ultrahigh resolution displays.
2Measurement precision
If the transistor area is reduced to increase pixel density, then the pixel density is improved, but manufacturing precision becomes more difficult
Solution Approach 1:
By moving electrode connections to the vertical dimension through stacked substrates, the lateral footprint of each transistor is reduced, enabling higher pixel density. The via holes provide precise vertical alignment paths that are less sensitive to lateral positioning errors, thereby maintaining manufacturing precision while increasing pixel density.
Solution Approach 2:
Via holes serve as intermediary structures that connect the source and drain electrodes across the insulating layer. These via holes provide a controlled and precise connection path that simplifies the manufacturing process by decoupling the alignment requirements, making it easier to achieve high pixel density without compromising manufacturing precision.
3Ease of manufacture
If conventional process routing is used, then the manufacturing process is simple, but short circuits occur in ultrahigh resolution displays
Solution Approach 1:
The patent adopts a stacked transistor architecture where source and drain electrodes are separated in the vertical dimension rather than relying on complex lateral routing. This approach maintains relative manufacturing simplicity by using standard deposition and etching processes to create via holes and stacked layers, while effectively preventing short circuits through vertical separation.
Data Source
AI summary
A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; the second source electrode is on a side of the metal oxide semiconductor layer close to the base substrate; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.