Display Sync Signal Generation with Clock Offset Compensation
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Solution Overview
Problem
Existing display devices face deviations in vertical synchronization signal frequency due to variations in clock signal frequency caused by temperature changes, leading to inaccuracies in synchronization.
Innovation Solution
A signal generator that calculates a clock offset by comparing frame clock numbers and generates horizontal and vertical synchronization signals based on this offset, compensating for temperature-induced deviations using a clock distribution block and compensation block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vertical synchronization signal is generated by counting horizontal synchronization signals, then the signal generation process is simple, but frequency deviation occurs due to temperature-induced clock signal variations
Solution Approach 1:
The patent applies preliminary action by calculating the clock offset in advance based on temperature information before generating the vertical synchronization signal. The signal generator pre-computes the offset value that compensates for temperature-induced clock frequency variations, then applies this offset during signal generation. This prevents frequency deviation rather than correcting it after occurrence, maintaining both simple signal generation process and high frequency accuracy.
2Use of energy by moving object
If clock signal frequency is reduced, then power consumption decreases, but frequency deviation between ideal and generated vertical synchronization signals increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the clock offset parameter based on temperature conditions. When temperature changes cause clock frequency drift, the signal generator modifies the offset value to compensate for the drift. This allows the system to maintain accurate vertical synchronization signal frequency across different operating conditions while using reduced clock signal frequencies for lower power consumption.
Data Source
AI summary
A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.