Display Sync Signal Generator for Temperature-Drift Compensation
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Solution Overview
Problem
Existing display devices experience deviations in the frequency of vertical synchronization signals due to variations in clock signal frequency caused by temperature changes, leading to inaccuracies in synchronization.
Innovation Solution
A signal generator that calculates a clock offset by comparing frame clock numbers and generates horizontal and vertical synchronization signals based on this offset, compensating for temperature-induced deviations without increasing the size or power consumption of the driving chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vertical synchronization signal is generated by counting horizontal synchronization signals, then the signal generation process is simple, but frequency deviation occurs due to temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the generated vertical synchronization signal frequency is continuously monitored and compared against the ideal frequency. Based on the detected deviation, the system adjusts the counting ratio or clock signal parameters to compensate for temperature-induced frequency drift, thereby maintaining accurate synchronization without complex additional circuitry
Solution Approach 2:
The patent dynamically changes operational parameters such as the counting ratio between horizontal and vertical synchronization signals or the clock signal frequency based on detected temperature variations. By adjusting these parameters in response to environmental conditions, the system maintains frequency accuracy while keeping the overall device structure simple
2Use of energy by moving object
If clock signal frequency is reduced, then power consumption decreases, but frequency deviation in vertical synchronization signal increases
Solution Approach 1:
The patent employs dynamic adjustment of the vertical synchronization signal generation parameters based on the actual clock signal frequency. When clock frequency varies due to power management or temperature changes, the system adaptively modifies the counting ratio or generation timing to maintain accurate vertical synchronization, ensuring both low power consumption and frequency precision
3Measurement precision
If additional circuitry like PLL or DLL is added to compensate for frequency deviation, then synchronization accuracy improves, but device complexity and power consumption increase
Solution Approach 1:
The patent enables the signal generation system to self-correct frequency deviations through built-in detection and adjustment mechanisms. The system monitors its own output frequency and automatically adjusts operational parameters to compensate for drift, eliminating the need for external PLL or DLL circuits while maintaining high synchronization accuracy
Solution Approach 2:
The patent combines the frequency detection and compensation functions directly into the existing vertical synchronization signal generation block. By integrating these functions rather than adding separate circuits, the system achieves accurate synchronization without increasing overall device complexity or power consumption
Data Source
AI summary
A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.