Multi-Display Synchronization via Timing Indication Feedback

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Solution Overview

Problem

Multiple display panels with varying refresh rates due to manufacturing variances operate asynchronously, leading to drift in relative phase and tearing effects when connected to the same host processor, which existing technologies fail to synchronize effectively without forcing all displays to a master clock.

Innovation Solution

The synchronization of multiple display panels is achieved by using timing indications from each display controller to delay refresh until all are ready, employing techniques like Adaptive Sync, and generating a trigger signal to maintain synchronization without relying on a master clock, allowing any display to be enabled or disabled without affecting synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple display panels operate with different refresh rates to accommodate manufacturing variances, then each display can operate at its optimal refresh rate, but the displays become asynchronous causing drift in relative phase and tearing effects

Engineering Contradiction:
Improverefresh rate flexibilityVSAvoiddisplay synchronization
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where each display controller provides a timing indication signal to the host processor, indicating when the display panel is ready for refresh. The host processor uses this feedback to dynamically adjust the refresh timing, ensuring all displays are synchronized without forcing them to a common master clock. This allows each display to operate at its optimal refresh rate while maintaining synchronization through continuous timing coordination.

Inventive Principle:
Principle #23Feedback

2Reliability

If a master clock is used to synchronize multiple display panels, then frame alignment can be maintained, but the system loses flexibility and cannot accommodate varying refresh rates

Engineering Contradiction:
Improveframe alignmentVSAvoidrefresh rate variation
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent employs dynamic timing adjustment where the host processor receives timing indications from each display controller and dynamically determines when to initiate refresh for each display. Instead of using a fixed master clock, the system adapts the refresh timing based on real-time status of each display panel, allowing different refresh rates while maintaining synchronization through flexible timing coordination.

Inventive Principle:
Principle #15Dynamics

3Reliability

If the host processor waits for all display controllers to indicate readiness before refreshing, then synchronization is maintained, but the refresh rate is limited by the slowest display

Engineering Contradiction:
ImprovesynchronizationVSAvoidrefresh rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary action by having each display controller prepare its timing indication in advance, allowing the host processor to understand when each display will be ready for refresh. This enables the host to coordinate refresh timing effectively, maintaining synchronization while optimizing the overall refresh rate by not being constrained by the slowest display alone.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3803844B1Multiple display synchronization
Publication Date: 2024.11.13 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3803844B1 patent drawingFigure 1~2
  • EP3803844B1 patent drawingFigure 3~4
  • EP3803844B1 patent drawingFigure 5

AI summary

A device (100) includes a plurality of display panels (102), a plurality of display controllers (116), each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication (134), and a processor (136) coupled to the plurality of display controllers to receive the timing indications from the plurality of display controllers. Each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel. The processor is configured to delay a refresh of the plurality of display panels until the timing indication is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels.