Display Driver TE Synchronization for Variable Refresh Switching
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Solution Overview
Problem
Existing electronic devices struggle to timely adjust the actual screen refresh frequency to match the image refresh frequency of the processor, leading to inconsistent display performance and increased complexity in logic processing.
Innovation Solution
Implementing a display drive with a fixed frequency TE signal that is a common multiple of supported screen refresh frequencies, allowing the processor to output display data at a variable frequency synchronized with the screen refresh frequency, enabling smooth stepless switching without additional commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TE signal frequency changes with screen refresh frequency, then the actual screen refresh frequency can respond to the image refresh frequency in a timely manner, but the device complexity increases due to needing to handle multiple frequency scenarios
Solution Approach 1:
The patent merges multiple frequency scenarios into a single unified logic processing path by using a fixed frequency TE signal that is a common multiple of all supported screen refresh frequencies. This allows the processor to handle frequency changes through a single set of frame switching drive logic without needing separate handling for each frequency scenario, thereby reducing device complexity while maintaining timely response.
Solution Approach 2:
The fixed frequency TE signal serves as a universal synchronization signal that works across all supported screen refresh frequencies. By designing the TE signal frequency as a common multiple (e.g., 360 Hz for frequencies including 1 Hz, 10 Hz, 20 Hz, 60 Hz, 90 Hz, and 120 Hz), the system achieves multi-functionality where a single signal generation and processing mechanism handles all frequency scenarios, reducing the need for additional commands and simplifying logic processing.
2Device complexity
If a fixed frequency TE signal is used, then logic processing complexity is reduced, but the ability to dynamically adjust to different refresh frequencies becomes more constrained
Solution Approach 1:
The patent changes the parameter of TE signal frequency from a variable that directly follows screen refresh frequency to a fixed value that is a common multiple of all supported frequencies. This parameter change simplifies the signal generation and processing logic while maintaining adaptability, as the fixed frequency signal can still synchronize with any supported refresh rate through integer division relationships.
Solution Approach 2:
The system uses periodic action by establishing a fixed frequency TE signal that periodically synchronizes frame switching across all supported refresh rates. The periodic nature of this fixed frequency signal (e.g., 360 Hz) allows it to naturally align with various screen refresh frequencies through integer relationships, providing both simplification and flexibility.
3Reliability
If the processor sends display data at variable frequency, then the actual screen refresh frequency can match the image refresh frequency, but additional commands are needed to change frequency which increases complexity
Solution Approach 1:
The patent extracts the frequency adjustment functionality from the command processing path by using a fixed frequency TE signal that inherently provides synchronization for all supported refresh rates. This removes the need for additional frequency change commands, as the fixed frequency signal automatically adapts to different screen refresh frequencies through its mathematical relationship (common multiple) with all supported rates, thereby reducing command processing complexity while maintaining synchronization accuracy.
Data Source
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AI summary
Embodiments of this application provide an electronic device and a driving method therefor, a display drive, and a processor, which relate to the field of electronic technologies, to cause an actual screen refresh frequency to respond to an image refresh frequency of a core processing chip like an upper-layer SOC in a timely manner. The electronic device includes a DDIC and an SOC. The DDIC is configured to send a TE signal, where a frequency of the TE signal is a first fixed frequency f1, and f1 is a common multiple of a plurality of screen refresh frequencies f supported by the electronic device. For example, if f supported by the electronic device includes 60 Hz, 90 Hz, and 120 Hz, f1 is 360 Hz. The SOC is configured to receive the TE signal, and output display data to the DDIC at a variable frequency f2, where f1=n×f2. In this case, a pulse period of f1 is a first pulse period T1, a pulse period of f2 is a second pulse period T2, and T2=n×T1. n is a ratio of f1 to f of a current frame. The second pulse period T2 of f2 of the current frame is always n times the first pulse period T1 of f1. To be specific, the display data is always sent once after n pieces of T1. n varies with f.