Display TEG Dummy Circuit Layout for Accurate TFT Measurement
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Solution Overview
Problem
In manufacturing display devices, it is challenging to accurately measure the electric characteristics of thin film transistors using test element groups (TEGs) due to the difficulty in replicating the semiconductor layer structure and shape of the display unit, as the number of semiconductor layers in TEGs is typically smaller, making it hard to obtain the same shape and structure as the display unit.
Innovation Solution
The display device incorporates a test element group with a test thin film transistor and dummy units in the peripheral area, featuring semiconductor layers and gate electrodes that overlap test pads, allowing for the formation of a semiconductor layer with the same shape and structure as the display unit, facilitating accurate electric characteristic measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a test element group (TEG) is formed with fewer semiconductor layers to simplify the testing structure, then the device complexity is reduced, but the manufacturing precision deteriorates because the semiconductor layer cannot achieve the same shape and structure as the display unit
Solution Approach 1:
The patent divides the test structure into multiple separate dummy units (first dummy unit, second dummy unit, third dummy unit) rather than using a single integrated test element group. Each dummy unit contains semiconductor layers with specific shapes that collectively represent different portions of the display unit's semiconductor layer structure. This segmentation allows the TEG to maintain structural simplicity while achieving comprehensive representation of the display unit's semiconductor layer characteristics through multiple discrete components.
2Ease of manufacture
If the number of semiconductor layers in TEG is reduced, then the ease of manufacture improves, but the measurement precision deteriorates because accurate electric characteristic measurement becomes difficult
Solution Approach 1:
Each dummy unit is designed with semiconductor layers having specific local shapes and configurations that correspond to particular regions or characteristics of the display unit's semiconductor layer. The first dummy unit, second dummy unit, and third dummy unit each provide localized structural representation, allowing accurate measurement of specific electric characteristics while maintaining overall manufacturing simplicity. This local quality approach ensures that each reduced component still contributes meaningfully to the overall measurement accuracy.
3Manufacturing precision
If dummy units are formed to overlap test pads, then the manufacturing precision of semiconductor layer structure is improved, but the device complexity increases due to additional overlapping structures
Solution Approach 1:
The patent merges the functional roles of the dummy units with the existing test pad structures by positioning the dummy units to overlap with the test pads. This merging allows the test pads to serve dual purposes: as electrical contact points and as structural references for the dummy units. The overlapping configuration enables the dummy units to achieve the desired semiconductor layer shape and structure representation while utilizing the existing test pad infrastructure, thereby reducing the need for completely separate structural elements.
Data Source
AI summary
A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.