Display Panel Test Circuit Layout for Narrow Bezel Pixel Testing
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Solution Overview
Problem
Current high PPI display products with narrow bezel designs face yield loss due to insufficient peripheral region area for complete test circuit arrangements, which are essential for testing the entire pixel array.
Innovation Solution
The electronic device incorporates a panel with a substrate featuring a test circuit that includes first and second switch devices connected to a common switch signal line, with conductive components overlapping the switch devices to optimize space usage within the limited peripheral region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the peripheral region area is increased to accommodate complete test circuits, then the test capability is improved, but the bezel width increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking conductive components over switch devices in the peripheral region. This three-dimensional arrangement allows test circuits to be accommodated within the limited planar area without increasing bezel width, effectively resolving the contradiction between test capability and bezel size.
Solution Approach 2:
The conductive components are nested over the switch devices, creating a compact vertical integration. This nesting approach maximizes space utilization in the peripheral region, enabling complete test circuits to fit within narrow bezel constraints while maintaining full test capability.
2Length of stationary object
If the peripheral region area is reduced for narrow bezel design, then the bezel width is decreased, but the test circuit area becomes insufficient
Solution Approach 1:
By transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking, the patent enables complete test circuits to be accommodated within reduced peripheral region area, thus achieving narrow bezel design without sacrificing test circuit functionality.
Solution Approach 2:
The patent merges multiple circuit elements (switch devices and conductive components) into a compact vertical structure. This consolidation reduces the horizontal space requirement of the peripheral region, enabling narrow bezel design while maintaining sufficient area for complete test circuits through efficient vertical integration.
3Reliability
If conventional test circuit arrangements are used, then the test circuit functionality is maintained, but the space efficiency is reduced
Solution Approach 1:
The patent employs vertical stacking of conductive components over switch devices, transforming the conventional two-dimensional test circuit layout into a three-dimensional structure. This dimensional change maintains full test circuit functionality while dramatically improving space efficiency in the peripheral region.
Solution Approach 2:
By nesting conductive components vertically over switch devices, the patent creates a compact integrated structure that preserves complete test circuit functionality while minimizing the peripheral region area required, thus achieving superior space efficiency compared to conventional arrangements.
Data Source
AI summary
An electronic device includes a panel. The panel includes a substrate, and a plurality of signal lines and a test circuit are disposed on the substrate. The test circuit includes a first switch device and a second switch device that are electrically connected to a same switch signal line. A first conductive component is connected between the first switch device and one of the signal lines. A second conductive component is connected between the second switch device and another one of the signal lines. The first conductive component and the second switch device are at least partially overlapped.