Display Device Test Unit ESD Protection via Segmentation
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Solution Overview
Problem
Electrostatic discharge (ESD) during the manufacturing process of display devices can damage semiconductor devices near the edges of the display device, particularly affecting the test units and leading to defects in the testing portion.
Innovation Solution
The display device incorporates a specific arrangement of transistors and test units around the display unit, with transistors connected to fan-out lines in a manner that minimizes the impact of ESD, allowing only one transistor per column to be exposed to ESD, and includes an electrostatic induction unit to maintain transistors in a turn-off state, reducing the likelihood of simultaneous damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If test units are arranged at the edge of the display device for effective testing, then testing capability is improved, but susceptibility to ESD damage increases
Solution Approach 1:
The test unit is divided into multiple transistors (first transistor, second transistor, third transistor, fourth transistor) arranged in a specific pattern. This segmentation allows the test functionality to be distributed across multiple components, reducing the impact of ESD damage on the entire test unit. Even if some transistors are damaged, others can continue to function.
Solution Approach 2:
The transistors are arranged asymmetrically with respect to their connection to fan-out lines. The first and third transistors are connected to the first fan-out line, while the second and fourth transistors are connected to the second fan-out line. This asymmetric arrangement ensures that not all transistors are exposed to ESD from the same direction, reducing the probability of simultaneous damage.
2Productivity
If multiple transistors are connected to the same fan-out line for efficient testing, then testing efficiency is improved, but the probability of simultaneous ESD damage increases
Solution Approach 1:
The test unit is segmented into multiple transistors connected to different fan-out lines. The first transistor and third transistor are connected to the first fan-out line, while the second transistor and fourth transistor are connected to the second fan-out line. This segmentation distributes the testing function across multiple independent connections, reducing the risk that ESD will damage all transistors simultaneously.
Solution Approach 2:
Each transistor is given a specific local arrangement and connection pattern. The transistors are positioned at different locations relative to the display device edges, with different exposure characteristics to ESD. This local quality differentiation ensures that ESD affecting one transistor does not necessarily affect others in the same test unit.
3Area of stationary object
If transistors are arranged close to the edge for compact design, then device compactness is improved, but ESD exposure increases
Solution Approach 1:
The transistors are arranged asymmetrically within the compact test unit structure. The first transistor is arranged closer to the first edge, the second transistor closer to the second edge, and so on. This asymmetric arrangement within a compact footprint ensures that even though the device is compact, the transistors are not all equally exposed to ESD from any single direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement reduces the probability of defectiveness in the test units due to ESD, enabling effective lighting and defect detection tests even if some transistors are damaged, thereby improving manufacturing efficiency and reducing display device defects.
Implementation Method 1
includes an electrostatic induction unit to maintain transistors in a turn-off state, reducing the likelihood of simultaneous damage
Data Source
AI summary
A display device includes a display unit that includes first pixels and second pixels alternately arranged in each of a first column and a third column, and third pixels arranged in a second column between the first column and the third column, wherein the first pixels and second pixels are alternately arranged in the third column in an order reverse to that of the first column. The display device includes a test unit in which first and second switches are coupled to columns including first pixels and second pixels alternatingly arranged. The first and second switches are spaced apart to prevent simultaneous damage from electrostatic discharge.