Display Substrate TFT Layout for Low-Leakage High-PPI Panels
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Solution Overview
Problem
High-PPI AR/VR display devices face challenges with TFTs using a single gate structure, leading to issues like large leakage current, gray-scale bright spots, flicker, and other defects.
Innovation Solution
A display substrate design with a TFT structure that mimics the double gate structure by using active layers with upper and lower laminated structures, along with gate electrodes and insulation layers, to reduce leakage current and improve image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a TFT with a single gate structure is used in high-PPI display panels, then the device complexity is reduced, but the leakage current increases significantly
Solution Approach 1:
The single gate structure is segmented into two separate gate structures (first gate and second gate), each controlling a portion of the channel. This segmentation allows independent control of different channel regions, enabling better suppression of leakage current while maintaining manageable device complexity through modular design
Solution Approach 2:
The invention transitions from a planar single-gate structure to a three-dimensional stacked dual-gate structure. By adding the vertical dimension with two gates positioned at different heights (first gate at lower position, second gate at upper position), the patent achieves enhanced control over the channel and reduced leakage current without excessively increasing lateral device footprint
2Ease of manufacture
If a TFT with a single gate structure is used, then the manufacturing process is simplified, but gray-scale bright spots and flicker defects occur
Solution Approach 1:
The channel is divided into two segments controlled by separate gates, allowing independent optimization of threshold voltages for different gray-scale ranges. This segmentation enables precise control over pixel activation and deactivation, eliminating gray-scale bright spots and flicker while maintaining a manufacturing process that builds upon standard single-gate techniques
Solution Approach 2:
The invention utilizes different threshold voltages for the first and second gates to control different aspects of pixel operation. By adjusting gate voltage parameters independently, the system achieves stable gray-scale performance and eliminates flicker defects, while the underlying manufacturing process remains compatible with established semiconductor fabrication methods
3Manufacturing precision
If the pixel size is reduced to achieve higher PPI, then the display resolution is improved, but the TFT structure becomes difficult to implement with traditional designs
Solution Approach 1:
By transitioning to a vertical stacked dual-gate configuration, the patent reduces the lateral footprint of each TFT. This vertical arrangement allows high-PPI pixel densities to be achieved without requiring excessively small lateral dimensions, making the TFT structure adaptable to high-resolution displays while maintaining manufacturability
Solution Approach 2:
The first gate and second gate are nested vertically within the same lateral footprint, with one gate positioned above the other. This nesting approach allows both gates to coexist in a compact space, enabling high pixel density while maintaining the dual-gate structure's functionality and avoiding excessive device complexity
Data Source
AI summary
The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a plurality of pixels arranged on the base substrate, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode laminated one on another. The source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer, and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer.