Display TFT Layout With Mixed Semiconductors for Mobility Stability
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Solution Overview
Problem
Current display apparatuses face challenges in achieving optimal mobility and stability in thin film transistors, particularly in oxide semiconductor transistors, which affect their performance in display devices due to variations in oxygen content and process conditions, and also struggle with uniformity and high manufacturing costs in polycrystalline silicon transistors.
Innovation Solution
A display apparatus design that includes thin film transistors with different semiconductor materials (polysilicon and oxide semiconductor) in display and non-display areas, with varying gate insulating layer thicknesses to manage mobility and stability, and uses a multilayer buffer structure to reduce moisture impact and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If oxide semiconductor thin film transistors are used, then manufacturing costs are reduced and transparency is achieved, but stability and electron mobility are degraded
Solution Approach 1:
The patent applies different gate insulating layer thicknesses to different functional regions: a first gate insulating layer with thickness of 50-150nm for switching TFTs in display areas, and a second gate insulating layer with thickness of 150-300nm for driving TFTs in non-display areas. This local differentiation optimizes both mobility for switching functions and stability for driving functions while maintaining oxide semiconductor advantages.
2Reliability
If polycrystalline silicon thin film transistors are used, then electron mobility and stability are improved, but manufacturing costs increase and uniformity is difficult to secure
Solution Approach 1:
The patent changes the gate insulating layer thickness parameter to differentiate transistor performance: thinner layers (50-150nm) for high-mobility switching TFTs and thicker layers (150-300nm) for stable driving TFTs. This parameter optimization allows oxide semiconductor TFTs to achieve performance levels previously only attainable with polycrystalline silicon, while maintaining lower manufacturing costs.
3Productivity
If amorphous silicon thin film transistors are used, then manufacturing process time is reduced, but current drivability and threshold voltage variation are inferior
Solution Approach 1:
The patent employs a composite gate insulating layer structure combining inorganic insulating layers (such as silicon oxide, silicon nitride, or silicon oxynitride) with controlled thicknesses. This composite approach enables oxide semiconductor TFTs to achieve superior current drivability and threshold voltage stability while maintaining the short manufacturing process time characteristic of amorphous silicon technology.
Data Source
AI summary
A display apparatus includes a first TFT in a display area including a first semiconductor pattern including a polysilicon, a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating layer is interposed, and first source and drain electrodes connected to the first semiconductor pattern, a second TFT in the display area including a second semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern under conditions that second and third gate insulating layers are interposed, second source and drain electrodes connected to the second semiconductor pattern, and a third TFT in a non-display area including a third semiconductor pattern including a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern under conditions that the third gate insulating layer is interposed, and third source and drain electrodes connected to the third semiconductor pattern.