Display TFT Test Substrate With Exposed Pin Access
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Solution Overview
Problem
Current methods for testing display substrates cannot accurately assess the electrical characteristics of thin film transistors, leading to instability in manufacturing processes and poor display performance due to the inability to directly test circuit structures in the active area.
Innovation Solution
A test substrate with defined test regions, thin film transistors, test holes, and test pins is created, allowing for the direct electrical testing of target thin film transistors by exposing their source, drain, or gate regions, and coupling test pins to these regions for voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If optical microscope or scanning electron microscope is used to inspect poor display regions, then structural inspection can be performed, but electrical characteristics of circuit structures cannot be tested
Solution Approach 1:
The substrate is divided into display regions and test regions. The test regions contain test circuit structures with exposed active regions that can be electrically contacted by probes, while display regions maintain their original structure. This segmentation allows simultaneous optical inspection of display regions and electrical testing of test regions, resolving the contradiction between structural inspection capability and electrical characteristics testing capability.
Solution Approach 2:
Test circuit structures serve as intermediaries between the substrate and testing equipment. These test structures include exposed active regions that can be contacted by probes, enabling electrical characteristics testing without affecting the display regions. The test structures act as a mediator that provides electrical access points while maintaining the integrity of the display area.
2Measurement precision
If test holes are formed to expose active regions for electrical testing, then electrical characteristics can be measured, but the substrate structure becomes more complex
Solution Approach 1:
The substrate is divided into display regions and test regions. Test holes are formed only in test regions to expose active regions of test circuit structures, while display regions remain unaffected. This localized approach enables electrical characteristics measurement without unnecessarily complicating the entire substrate structure.
Solution Approach 2:
Different regions of the substrate have different structures optimized for their specific functions. Test regions contain holes and exposed active regions for electrical testing, while display regions maintain their original high-quality structure for optimal display performance. This local differentiation allows electrical measurement capability without globally increasing complexity.
3Reliability
If manufacturing process is improved through electrical testing, then display performance can be enhanced, but testing capability must be integrated into the manufacturing process
Solution Approach 1:
Test circuit structures are formed during the manufacturing process before the final display structure is completed. This preliminary action allows electrical characteristics testing to be performed on test structures using the same thin film transistor fabrication processes, enabling manufacturing process optimization without requiring separate testing equipment or additional complex steps.
Solution Approach 2:
The test circuit structures use the same thin film transistor fabrication processes as the display structures, making the manufacturing process universal. The same deposition, etching, and doping techniques used for display TFTs are also used to create test structures, allowing electrical testing capability to be integrated into the existing manufacturing process without adding significant complexity.
Data Source
AI summary
A test substrate has at least one test region and includes a base substrate, a plurality of thin film transistors disposed on the base substrate, at least one test hole located in the test region, and at least one test pin. At least one of the thin film transistors is a target thin film transistor to be tested, each target thin film transistor is located in one test region. Each test hole exposes a source region, a drain region or a gate of a corresponding target thin film transistor at a bottom thereof. Each test pin is located in one test hole. One end of the test pin passes through the test hole to be coupled to the source region, the drain region or the gate of the corresponding target thin film transistor, and another end of the test pin is exposed at a surface of the test substrate.