Display Time Code Synchronization for Shared Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display systems using shared links face synchronization challenges due to varying latency and independent clock domains between display transmitters and panels, leading to potential overflow or underflow issues.
Innovation Solution
Implementing a Display Time Code (DTC) mechanism to adjust the display panel's clock frequency and synchronize it with the display transmitter's clock frequency, using DTC generators and frequency adjusters, and compensating for variable latency through strobe signals or transmission delay calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a shared link is used to transport display data, then link versatility and resource sharing are improved, but synchronization reliability deteriorates due to variable latency
Solution Approach 1:
The patent implements a feedback mechanism where the display panel continuously monitors the arrival time of display time codes relative to its own clock cycles, detects drift between transmitter and panel clock frequencies, and adjusts its clock frequency accordingly to maintain synchronization despite variable latency on the shared link
Solution Approach 2:
The patent dynamically changes the clock frequency parameter of the display panel based on detected drift, allowing the system to adapt to varying latency conditions on the shared link while maintaining synchronization between transmitter and panel
2Adaptability or versatility
If independent clock domains are used between transmitter and panel, then device independence is improved, but clock synchronization deteriorates due to frequency drift
Solution Approach 1:
The display panel uses feedback from comparing received display time codes with its own locally generated time codes to detect frequency drift between independent clock domains, then adjusts its clock frequency to eliminate the drift and maintain synchronization
Solution Approach 2:
Each device (transmitter and panel) maintains its own independent clock domain and generates its own display time codes, with the panel autonomously adjusting its clock frequency based on detected drift, eliminating the need for a dedicated synchronization link
3Device complexity
If no dedicated synchronization link is used, then system complexity is reduced, but measurement precision of latency deteriorates
Solution Approach 1:
The patent combines data transmission and synchronization functions into a single shared link, eliminating the need for a separate dedicated synchronization link while maintaining precise latency measurement through the display time code mechanism
Solution Approach 2:
The shared link serves multiple functions including data transmission and synchronization signaling, allowing the system to reduce complexity while maintaining precise latency measurement through the display time codes transmitted over the same link
Data Source
AI summary
Techniques for synchronizing a display transmitter and display panel are described. An example display panel includes a timing controller to receive display data from a transmitter and render the display data on a display screen of the display panel. The display panel is in a first clock domain and the transmitter is in a second clock domain which is derived separately from the first clock domain. The display panel also includes a time code generator to generate a first display time code and a frequency adjuster to receive a second display time code from the transmitter. The frequency adjuster adjusts the clock frequency of the display panel based on the first display time code and the second display time code.