Display Timing Control Circuit Adjustable Clock Divisor
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Solution Overview
Problem
Conventional display timing control methods often result in incomplete scan lines due to forced synchronization of output v-sync signals, leading to undesirable display effects, especially in low timing tolerance devices.
Innovation Solution
A display timing control circuit comprising an output pixel clock generator, a display timing generator, and a clock adjusting unit that adjusts the clock divisor based on frequency and phase differences between input and output vertical reference signals to achieve accurate frame synchronization, using a clock synthesizer, phase lock loop, frequency difference detector, phase difference detector, and clock divisor generator to generate updated pixel clock and vertical reference signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the output v-sync signal is forced to change to synchronize with the input v-sync signal, then frame synchronization is achieved, but incomplete scan lines occur causing undesirable display effects
Solution Approach 1:
The patent applies preliminary action by detecting the phase difference between input and output v-sync signals in advance, calculating the required clock divisor adjustment before the next frame starts, and preparing the corrected output pixel clock signal. This ensures that the display timing is adjusted proactively rather than reactively, preventing incomplete scan lines while maintaining frame synchronization.
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase difference between input and output vertical reference signals, using this feedback to dynamically adjust the clock divisor, and generating corrected clock signals that compensate for timing deviations. This closed-loop control ensures accurate frame synchronization while preventing display artifacts.
2Reliability
If the output v-sync is reset to force synchronization with input v-sync, then frame rate synchronization is achieved, but the present output cycle cannot be completed
Solution Approach 1:
The patent applies dynamics by making the clock divisor adjustable rather than fixed. The system dynamically changes the clock divisor based on detected phase differences, allowing the output pixel clock frequency to be fine-tuned in real-time. This dynamic adjustment enables the system to maintain complete output cycles while achieving frame rate synchronization with the input signal.
3Device complexity
If conventional display timing control is used, then simple control logic is maintained, but display timing accuracy deteriorates
Solution Approach 1:
The patent introduces intermediary components including a phase difference detector, frequency difference detector, and clock divisor generator that act as mediators between the input v-sync signal and the output pixel clock generator. These intermediaries precisely measure timing deviations and calculate appropriate corrections, significantly improving display timing accuracy while adding manageable complexity to the control system.
Data Source
AI summary
A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.