Display Timing Controller Adjusts Clock Active Period for Luminance Uniformity

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Solution Overview

Problem

Display devices with non-square shapes or opening patterns experience luminance uniformity issues due to load differences across scan lines, leading to varying data writing times and reduced luminance in areas with fewer pixels.

Innovation Solution

A display device with a timing controller that adjusts the width of the active period of the clock signal based on the number and length of pixel rows, ensuring scan signals have consistent active periods across the panel, regardless of shape or opening patterns, thereby uniformizing data writing times and luminance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a display panel has an opening pattern or non-square shape, then the device complexity is reduced and adaptability is improved, but luminance uniformity deteriorates due to load differences across scan lines

Engineering Contradiction:
Improvedisplay panel shape adaptabilityVSAvoidluminance uniformity
Core Design Contradiction:
Adaptability or versatilityVSIllumination intensity

Solution Approach 1:

The patent applies local quality by dividing the display panel into multiple regions (first region with opening pattern, second region without opening pattern) and applying different clock signal active period widths to each region. The timing controller adjusts the clock signal parameters locally for each region based on the pixel row length and load characteristics, ensuring that each region receives appropriately tailored timing parameters to achieve uniform luminance across the entire panel despite structural differences.

Inventive Principle:
Principle #3Local quality

2Illumination intensity

If the clock signal active period is adjusted for different pixel row lengths, then luminance uniformity is improved, but device complexity increases due to additional timing control requirements

Engineering Contradiction:
Improveluminance uniformityVSAvoidtiming control complexity
Core Design Contradiction:
Illumination intensityVSDevice complexity

Solution Approach 1:

The patent implements parameter changes by dynamically adjusting the active period width of the clock signal based on the pixel row length and region characteristics. The timing controller modifies the clock signal parameters (active period width) according to the specific requirements of each region, allowing the system to adapt to different panel configurations and maintain luminance uniformity through parameter optimization rather than structural changes.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If scan signals are provided to all pixel rows with the same clock signal, then device complexity is minimized, but data writing time uniformity deteriorates leading to luminance differences

Engineering Contradiction:
Improvesignal generation complexityVSAvoiddata writing time uniformity
Core Design Contradiction:
Device complexityVSDuration of action of moving object

Solution Approach 1:

The patent applies dynamics by making the clock signal characteristics dynamic rather than static. The timing controller adjusts the active period width of the clock signal dynamically based on the pixel row length and region-specific load characteristics. This dynamic adjustment ensures that scan signals are provided with appropriate timing parameters for each region, achieving uniform data writing time across all pixel rows while adapting to the specific structural requirements of each region.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10395599B2Display device
Publication Date: 2019.08.27 SAMSUNG DISPLAY CO LTD
  • US10395599B2 patent drawing
  • US10395599B2 patent drawing
  • US10395599B2 patent drawing

AI summary

A display device according to example embodiments includes a display panel divided into a first area including a plurality of first area pixel rows and a second area including a plurality of second area pixel rows, the number of pixels of each of the second area pixel rows being less than the number of pixels of each of the first area pixel rows, a scan driver configured to provide a plurality of scan signals to the display panel based on a width of an active period of a clock signal, the scan signals being output having substantially the same width of active periods to each other, a data driver configured to provide a plurality of data signals to the display panel, and a timing controller configured to adjust the width of the active period of the clock signal within a frame period based on locations of the first area and the second area.