Display Timing Controller Dynamic Clock Slew Rate Noise Reduction
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Solution Overview
Problem
Current display devices face challenges in reducing RF noise while maintaining signal integrity and optimizing power consumption, particularly in the transition between active and blank sections during image display, due to differences in clock signal slew rates.
Innovation Solution
A display device and method that utilize a timing controller to generate a first clock signal with a shorter rising time and higher slew rate during active sections and a second clock signal with a longer rising time and lower slew rate during blank sections, allowing for efficient data signal transmission and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock signal with high slew rate is used during active section, then data signal transmission speed is improved, but RF noise increases
Solution Approach 1:
The patent applies dynamics by changing the slew rate of the clock signal based on the operational section. During the active section, a high slew rate clock signal is used to ensure fast data transmission, while during the blank section, the slew rate is reduced to minimize RF noise generation. This dynamic adjustment resolves the contradiction between transmission speed and noise generation.
Solution Approach 2:
The patent changes the parameter of slew rate of the clock signal according to the section type. By adjusting this key parameter dynamically between high (active section) and low (blank section), the system achieves both fast data transmission when needed and reduced RF noise when not needed, resolving the technical contradiction.
2Productivity
If a clock signal with short rising time is used during active section, then data signal transmission efficiency is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the rising time of the clock signal based on the operational section. During the active section, a short rising time is used to maximize transmission efficiency, while during the blank section, the rising time is extended to reduce power consumption. This dynamic behavior resolves the contradiction between efficiency and energy usage.
Solution Approach 2:
The patent changes the rising time parameter of the clock signal according to the section type. By setting a short rising time during active sections for efficiency and a longer rising time during blank sections for lower power consumption, the system resolves the contradiction between productivity and energy consumption.
3Reliability
If a clock signal with high slew rate is used during blank section, then signal integrity is maintained, but RF noise increases
Solution Approach 1:
The patent applies dynamics by adjusting the slew rate of the clock signal based on the operational section. During the blank section, the slew rate is reduced to minimize RF noise generation while maintaining sufficient signal integrity for proper display operation. This dynamic adjustment resolves the contradiction between signal integrity and noise generation.
Solution Approach 2:
The patent changes the slew rate parameter of the clock signal according to the section type. By reducing the slew rate during blank sections, the system minimizes RF noise while maintaining adequate signal integrity, resolving the technical contradiction between reliability and harmful factors.
Data Source
AI summary
A display device includes a timing controller, a driver, and a display panel. The timing controller outputs a first clock signal having first rising time during an active section and a second clock signal having second rising time during a blank section adjacent to the active section. The driver generates a data signal based on the first clock signal and the second clock signal and to output the data signal. The display panel displays an image based on the data signal. The first rising time is shorter than the second rising time.