Display Timing Controller Frequency Adjustment for Kickback Voltage
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Solution Overview
Problem
Display devices suffer from image quality deterioration due to kickback voltage caused by parasite capacitance between the gate and drain electrodes of thin film transistors, leading to brightness differences in specific image patterns.
Innovation Solution
A display device with a timing controller that adjusts the frequency of the vertical sync start signal when the image signal of a current frame is identical to the previous frame, generating a data enable signal with an active and blank interval, and outputs a parallel sync start signal to the data driver, effectively reducing the impact of kickback voltage by synchronizing the image signal with the vertical sync start signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display device uses a conventional fixed frequency vertical sync start signal, then the gate driver operates stably, but kickback voltage causes brightness differences and image quality deterioration
Solution Approach 1:
The patent applies dynamics by making the vertical sync start signal frequency variable rather than fixed. The timing controller dynamically adjusts the frequency based on whether the current frame image is identical to the previous frame, allowing the system to adapt to different display conditions and minimize kickback voltage effects while maintaining stable operation.
Solution Approach 2:
The patent changes the frequency parameter of the vertical sync start signal to eliminate kickback voltage effects. When the current frame image is identical to the previous frame, the timing controller changes the frequency from a first frequency to a second frequency, thereby altering the timing characteristics to prevent brightness differences caused by kickback voltage.
2Reliability
If the frequency of vertical sync start signal is changed to reduce kickback voltage, then brightness differences are minimized, but the complexity of the timing controller increases
Solution Approach 1:
The patent implements feedback by having the timing controller compare the current frame image with the previous frame image and adjust the vertical sync start signal frequency accordingly. This closed-loop control ensures that frequency changes are made only when necessary (when images are identical), automatically eliminating kickback voltage effects while maintaining simple operation for normal cases.
Solution Approach 2:
The patent changes the frequency parameter of the vertical sync start signal based on image comparison results. The timing controller monitors image changes and adjusts the frequency parameter dynamically, adding minimal complexity only when image identical conditions are detected, while maintaining conventional operation for all other cases.
3Object-affected harmful factors
If the vertical sync start signal frequency is adjusted dynamically, then kickback voltage effects are reduced, but the synchronization between gate driver and image signal becomes more complex
Solution Approach 1:
The patent applies dynamics by making the vertical sync start signal frequency adaptive rather than fixed. The timing controller dynamically adjusts the frequency based on real-time image comparison, allowing the system to respond to actual display conditions and minimize kickback voltage while maintaining straightforward synchronization through automatic adaptation.
Solution Approach 2:
The patent implements feedback control where the timing controller continuously monitors image changes and adjusts the vertical sync start signal frequency accordingly. This feedback mechanism simplifies synchronization by automatically adapting to image conditions, eliminating the need for complex manual synchronization adjustments while reducing kickback voltage effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves display quality by minimizing brightness differences and reducing the recognition of kickback voltage effects, maintaining image consistency across frames.
Implementation Method 1
due to a parasite capacitance between the gate electrode and the drain electrode of the thin film transistor resulting from manufacturing processes of the display panel, an actual grayscale voltage applied to the liquid crystal capacitor and the storage capacitor may be distorted
Data Source
AI summary
A display device includes: a display panel including gate lines, a data lines crossing the gate lines, and pixels connected to the data lines and the gate lines; a data driver configured to drive the data lines; a gate driver configured to drive the gate lines in synchronization with a vertical sync start signal; and a timing controller configured to control the data driver and the gate driver in response to an image signal and a control signal inputted thereto from an outside, where the timing controller outputs the vertical sync start signal to the gate driver, and changes a frequency of the vertical sync start signal when an image signal of a current frame is identical to an image signal shifted from an image signal of a previous frame in a first direction.